Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7372102 | Structure having a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology | Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang | 2008-05-13 |
| 7250344 | Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology | Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang | 2007-07-31 |
| 7015086 | Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology | Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang | 2006-03-21 |
| 6747336 | Twin current bipolar device with hi-lo base profile | Ruey-Hsing Liu, Chiou-Shian Peng, Kuo-Chio Liu | 2004-06-08 |
| 6569730 | High voltage transistor using P+ buried layer | Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu | 2003-05-27 |
| 6423590 | High voltage transistor using P+ buried layer | Ruey-Hsin Lin, Jei-Feng Hwang, Kuo-Chio Liu | 2002-07-23 |
| 6396126 | High voltage transistor using P+ buried layer | Ruey-Hsin Liu, Jyh-Min Jiang, Jei-Feng Hwang | 2002-05-28 |
| 6340833 | Integrated circuit polysilicon resistor having a silicide extension to achieve 100 % metal shielding from hydrogen intrusion | Ruey-Hsin Liu, Yung-Lung Hsu | 2002-01-22 |
| 6245609 | High voltage transistor using P+ buried layer | Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu | 2001-06-12 |
| 6242313 | Use of polysilicon field plates to improve high voltage bipolar device breakdown voltage | Jei-Feng Hwang, Ruey-Hsin Liou, Jyh-Min Jiang | 2001-06-05 |
| 6211028 | Twin current bipolar device with hi-lo base profile | Ruey-Hsing Liu, Chiou-Shian Peng, Kuo-Chio Liu | 2001-04-03 |
| 6165861 | Integrated circuit polysilicon resistor having a silicide extension to achieve 100% metal shielding from hydrogen intrusion | Ruey-Hsin Liu, Yung-Lung Hsu | 2000-12-26 |
| 6162695 | Field ring to improve the breakdown voltage for a high voltage bipolar device | Jei-Feng Hwang, Ruey-Hsin Liou, Kuo-Chio Liu | 2000-12-19 |
| 6096629 | Uniform sidewall profile etch method for forming low contact leakage schottky diode contact | Yen-Shih Ho | 2000-08-01 |