Issued Patents All Time
Showing 1–25 of 156 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176407 | Method of forming a transistor device with a gate structure having a pair of recess regions and a resistive protection layer within | Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei +2 more | 2024-12-24 |
| 12132108 | Dual gate structures for semiconductor devices | Po-Chih Su, Pei-Lun Wang, Jia-Rui Lee, Jyun-Guan Jhou | 2024-10-29 |
| 12074208 | Method of making triple well isolated diode | Chih-Chang Cheng, Fu-Yu Chu | 2024-08-27 |
| 12027526 | Breakdown voltage capability of high voltage device | Hsin-Chih Chiang, Tung-Yang Lin, Ming-Ta Lei | 2024-07-02 |
| 11967645 | Power MOSFETs structure | Yogendra Yadav, Chi-Chih Chen, Chih-Wen Yao | 2024-04-23 |
| 11923429 | Plate design to decrease noise in semiconductor devices | Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Shih-Fen Huang | 2024-03-05 |
| 11894459 | Dual gate structures for semiconductor devices | Po-Chih Su, Pei-Lun Wang, Jia-Rui Lee, Jyun-Guan Jhou | 2024-02-06 |
| 11817396 | Layout to reduce noise in semiconductor devices | Chih-Chang Cheng, Fu-Yu Chu | 2023-11-14 |
| 11769812 | Semiconductor device having multiple wells and method of making | Chih-Chang Cheng, Fu-Yu Chu | 2023-09-26 |
| 11757034 | High voltage device | Hung-Sen Wang, Yun-Ta Tsai, Shih-Fen Huang, Ho-Chun Liou | 2023-09-12 |
| 11676997 | High voltage resistor with high voltage junction termination | Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng | 2023-06-13 |
| 11538914 | Semiconductor device | Ta-Yuan Kung, Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei | 2022-12-27 |
| 11532701 | Semiconductor isolation structure and method for making the semiconductor isolation structure | Hsin Fu Lin, Tsung-Hao Yeh, Chien-Hung Liu, Shiang-Hung Huang, Chih-Wei Hung +2 more | 2022-12-20 |
| 11508757 | Breakdown voltage capability of high voltage device | Hsin-Chih Chiang, Tung-Yang Lin, Ming-Ta Lei | 2022-11-22 |
| 11444169 | Transistor device with a gate structure having recesses overlying an interface between isolation and device regions | Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei +2 more | 2022-09-13 |
| 11437466 | Avalanche-protected transistors using a bottom breakdown current path and methods of forming the same | Liang-Yu Su, Hung-Chih Tsai, Ming-Ta Lei, Chang-Tai YANG, Te-Yin Hsia +2 more | 2022-09-06 |
| 11424244 | Integrated circuit having a vertical power MOS transistor | Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su | 2022-08-23 |
| 11322609 | High voltage device | Hung-Sen Wang, Yun-Ta Tsai, Shih-Fen Huang, Ho-Chun Liou | 2022-05-03 |
| 11158739 | Semiconductor structure having field plate and associated fabricating method | Chih-Chang Cheng, Fu-Yu Chu, Kuang-Hsin Chen, Chih-Hsin Ko, Shih-Fen Huang | 2021-10-26 |
| 11107899 | Plate design to decrease noise in semiconductor devices | Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Shih-Fen Huang | 2021-08-31 |
| 11088277 | Power MOSFETs structure | Yogendra Yadav, Chi-Chih Chen, Chih-Wen Yao | 2021-08-10 |
| 11088085 | Layout to reduce noise in semiconductor devices | Chih-Chang Cheng, Fu-Yu Chu | 2021-08-10 |
| 11031495 | Apparatus and method for power MOS transistor | Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su | 2021-06-08 |
| 11011610 | Plate design to decrease noise in semiconductor devices | Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Shih-Fen Huang | 2021-05-18 |
| 10985256 | Semiconductor device and method for manufacturing the same | Ta-Yuan Kung, Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei | 2021-04-20 |