Issued Patents All Time
Showing 26–50 of 156 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10957772 | Semiconductor device having multiple wells | Chih-Chang Cheng, Fu-Yu Chu | 2021-03-23 |
| 10840246 | Integrated circuit having a vertical power MOS transistor | Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su | 2020-11-17 |
| 10727334 | Lateral DMOS device with dummy gate | Chun-Wai Ng, Jun Cai, Hsueh-Liang Chou, Chi-Chih Chen | 2020-07-28 |
| 10714432 | Layout to reduce noise in semiconductor devices | Chih-Chang Cheng, Fu-Yu Chu | 2020-07-14 |
| 10686032 | High voltage resistor with high voltage junction termination | Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng | 2020-06-16 |
| 10686065 | Apparatus and method for power MOS transistor | Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su | 2020-06-16 |
| 10686047 | Semiconductor device and method for manufacturing the same | Ta-Yuan Kung, Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei | 2020-06-16 |
| 10680100 | Field structure and methodology | Po-Chih Su, Hsueh-Liang Chou | 2020-06-09 |
| 10680019 | Selective polysilicon doping for gate induced drain leakage improvement | Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei | 2020-06-09 |
| 10672904 | Power MOSFETs and methods for manufacturing the same | Yogendra Yadav, Chi-Chih Chen, Chih-Wen Yao | 2020-06-02 |
| 10658482 | Plate design to decrease noise in semiconductor devices | Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Shih-Fen Huang | 2020-05-19 |
| 10510880 | Trench power MOSFET | Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su | 2019-12-17 |
| 10497795 | Triple well isolated diode and method of making | Chih-Chang Cheng, Fu-Yu Chu | 2019-12-03 |
| 10453955 | Lateral DMOS device with dummy gate | Chun-Wai Ng, Jun Cai, Hsueh-Liang Chou, Chi-Chih Chen | 2019-10-22 |
| 10381259 | Semiconductor device with localized carrier lifetime reduction and fabrication method thereof | Alex Kalnitsky, Chih-Wen Yao, Jun Cai, Hsiao-Chin Tuan | 2019-08-13 |
| 10304829 | Integrated circuit having a vertical power MOS transistor | Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su | 2019-05-28 |
| 10276596 | Selective polysilicon doping for gate induced drain leakage improvement | Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei | 2019-04-30 |
| 10269954 | Power MOSFETs and methods for manufacturing the same | Yogendra Yadav, Chi-Chih Chen, Chih-Wen Yao | 2019-04-23 |
| 10205024 | Semiconductor structure having field plate and associated fabricating method | Chih-Chang Cheng, Fu-Yu Chu, Kuang-Hsin Chen, Chih-Hsin Ko, Shih-Fen Huang | 2019-02-12 |
| 10170589 | Vertical power MOSFET and methods for forming the same | Po-Chih Su, Hsueh-Liang Chou, Chun-Wai Ng | 2019-01-01 |
| 10164085 | Apparatus and method for power MOS transistor | Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su | 2018-12-25 |
| 10141421 | Vertical power MOSFET and methods of forming the same | Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su | 2018-11-27 |
| 10109732 | Trench power MOSFET | Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su | 2018-10-23 |
| 10103223 | High voltage resistor with pin diode isolation | Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng | 2018-10-16 |
| 10090390 | FinFET with trench field plate | Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su | 2018-10-02 |