Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12074208 | Method of making triple well isolated diode | Chih-Chang Cheng, Ruey-Hsin Liu | 2024-08-27 |
| 11923429 | Plate design to decrease noise in semiconductor devices | Chih-Chang Cheng, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang | 2024-03-05 |
| 11817396 | Layout to reduce noise in semiconductor devices | Chih-Chang Cheng, Ruey-Hsin Liu | 2023-11-14 |
| 11769812 | Semiconductor device having multiple wells and method of making | Chih-Chang Cheng, Ruey-Hsin Liu | 2023-09-26 |
| 11158739 | Semiconductor structure having field plate and associated fabricating method | Chih-Chang Cheng, Ruey-Hsin Liu, Kuang-Hsin Chen, Chih-Hsin Ko, Shih-Fen Huang | 2021-10-26 |
| 11107899 | Plate design to decrease noise in semiconductor devices | Chih-Chang Cheng, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang | 2021-08-31 |
| 11088085 | Layout to reduce noise in semiconductor devices | Chih-Chang Cheng, Ruey-Hsin Liu | 2021-08-10 |
| 11011610 | Plate design to decrease noise in semiconductor devices | Chih-Chang Cheng, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang | 2021-05-18 |
| 10957772 | Semiconductor device having multiple wells | Chih-Chang Cheng, Ruey-Hsin Liu | 2021-03-23 |
| 10714432 | Layout to reduce noise in semiconductor devices | Chih-Chang Cheng, Ruey-Hsin Liu | 2020-07-14 |
| 10658482 | Plate design to decrease noise in semiconductor devices | Chih-Chang Cheng, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang | 2020-05-19 |
| 10497795 | Triple well isolated diode and method of making | Chih-Chang Cheng, Ruey-Hsin Liu | 2019-12-03 |
| 10205024 | Semiconductor structure having field plate and associated fabricating method | Chih-Chang Cheng, Ruey-Hsin Liu, Kuang-Hsin Chen, Chih-Hsin Ko, Shih-Fen Huang | 2019-02-12 |
| 10038090 | Power MOSFETs and methods for forming the same | Chih-Chang Cheng, Tung-Yang Lin, Ruey-Hsin Liu | 2018-07-31 |
| 9917168 | Metal oxide semiconductor field effect transistor having variable thickness gate dielectric | Chih-Chang Cheng, Ruey-Hsin Liu | 2018-03-13 |
| 9917212 | JFET structure and manufacturing method of the same | Chih-Chang Cheng, Ruey-Hsin Liu | 2018-03-13 |
| 9601616 | Power MOSFETs and methods for forming the same | Chih-Chang Cheng, Tung-Yang Lin, Ruey-Hsin Liu | 2017-03-21 |
| 9583618 | Metal oxide semiconductor field effect transistor having asymmetric lightly doped drain regions | Chih-Chang Cheng, Ruey-Hsin Liu | 2017-02-28 |
| 9583610 | Transistor and method of manufacturing the same | Chih-Chang Cheng, Ruey-Hsin Liu | 2017-02-28 |
| 9520467 | Field effect transistor structure and manufacturing method thereof | Chih-Chang Cheng, Ruey-Hsin Liu | 2016-12-13 |
| 9472665 | MOS transistor and method for manufacturing MOS transistor | Chih-Chang Cheng, Ruey-Hsin Liu | 2016-10-18 |
| 9466715 | MOS transistor having a gate dielectric with multiple thicknesses | Chih-Chang Cheng, Ruey-Hsin Liu | 2016-10-11 |
| 9391159 | Triple well isolated diode and method of making | Chih-Chang Cheng, Ruey-Hsin Liu | 2016-07-12 |
| 9356139 | Power MOSFETs and methods for forming the same | Chih-Chang Cheng, Tung-Yang Lin, Ruey-Hsin Liu | 2016-05-31 |
| 9159827 | Transistor and method of manufacturing the same | Chih-Chang Cheng, Ruey-Hsin Liu | 2015-10-13 |