Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406942 | Semiconductor device | Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen | 2025-09-02 |
| 11791285 | Semiconductor device | Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen | 2023-10-17 |
| 11757034 | High voltage device | Hung-Sen Wang, Yun-Ta Tsai, Ruey-Hsin Liu, Shih-Fen Huang | 2023-09-12 |
| 11322609 | High voltage device | Hung-Sen Wang, Yun-Ta Tsai, Ruey-Hsin Liu, Shih-Fen Huang | 2022-05-03 |
| 11011478 | Semiconductor device | Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen | 2021-05-18 |
| 10930599 | Semiconductor device and manufacturing method thereof | Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen | 2021-02-23 |
| 10714384 | Semiconductor device and manufacturing method thereof | Ming-Hui Yang, Chun-Ting Liao, Chen-Yuan Chen, Yi-Te Chen | 2020-07-14 |
| 10373865 | Semiconductor device and manufacturing method thereof | Ming-Hui Yang, Chun-Ting Liao, Chen-Yuan Chen, Yi-Te Chen | 2019-08-06 |
| 10366956 | Semiconductor device and manufacturing method thereof | Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen | 2019-07-30 |
| 9553140 | Integrated circuit and method of fabricating the same | Hung-Sen Wang, Shih-Chi Yang, Kuo-Ching Chang, Wei-Sho Hung | 2017-01-24 |
| 9331136 | Integrated circuit and method of fabricating the same | Hung-Sen Wang, Shih-Chi Yang, Kuo-Ching Chang, Wei-Sho Hung | 2016-05-03 |
| 6930926 | Method for erasing a flash EEPROM | Yu-Shen Lin, Shin-Jang Shen, Chun-Hsiung Hung, Shuo-Nan Hung | 2005-08-16 |
| 6845052 | Dual reference cell sensing scheme for non-volatile memory | Hsin-Yi Ho, Nai-Ping Kuo, Chun-Hsiung Hung, Gin-Liang Chen, Wen-Chiao Ho | 2005-01-18 |
| 6665216 | Apparatus and system for reading non-volatile memory with dual reference cells | Hsin-Yi Ho, Nai-Ping Kuo, Chun-Hsiung Hung, Gin-Laing Chen, Wen-Chiao Ho | 2003-12-16 |
| 6618848 | Method for designing circuit layout of non-neighboring metal bit lines to reduce coupling effect | Han-Sung Chen, Kuo-Yu Liao, Yung-Feng Lin, Chun-Hsiung Hung | 2003-09-09 |
| 6580287 | Voltage-boosting generator for reducing effects due to operating voltage variation and temperature change | Hsien-Wen Hsu, Yu-Shen Lin, Chun-Hsiung Hung | 2003-06-17 |
| 6563735 | NOR-structured semiconductor memory device | Hsin-Chien Chen, Gin-Liang Chen, Hsin-Yi Ho, Chun-Hsiung Hung | 2003-05-13 |
| 6421267 | Memory array architecture | Nai-Ping Kuo, Hsin-Yi Ho, Chun-Hsiung Hung | 2002-07-16 |
| 6396753 | Method and structure for testing embedded flash memory | Chun-Hsiung Hung, Nai-Ping Kuo, Tu-Shun Chen | 2002-05-28 |
| 6385097 | Method for tracking metal bit line coupling effect | Kuo-Yu Liao, Han-Sung Chen, Chun-Hsiung Hung | 2002-05-07 |
| 5233562 | Methods of repairing field-effect memory cells in an electrically erasable and electrically programmable memory device | Tong-Chern Ong, Gregory E. Atwood | 1993-08-03 |