Issued Patents All Time
Showing 1–25 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12277346 | Memory system having planes with multibit status | Nai-Ping Kuo, Chien-Hsin Liu | 2025-04-15 |
| 12131787 | Page buffer counting for in-memory search | E-Yuan Chang, Ji-Yu Hung | 2024-10-29 |
| 12020741 | Managing data refresh in semiconductor devices | — | 2024-06-25 |
| 12014798 | In memory data computation and analysis | Chun-Hsiung Hung | 2024-06-18 |
| 11853567 | Data retention in memory devices | E-Yuan Chang | 2023-12-26 |
| 11815995 | Redundancy schemes for repairing column defects | Che-Wei Liang, Hung-Wei Lu, Ming-Cheng Tu | 2023-11-14 |
| 11782824 | Universal data path architecture for different data array | — | 2023-10-10 |
| 11755399 | Bit error rate reduction technology | Chun-Hsiung Hung | 2023-09-12 |
| 11742004 | Memory supporting multiple types of operations | Nai-Ping Kuo, Chien-Hsin Liu | 2023-08-29 |
| 11734181 | Continuous read with multiple read commands | Chun-Lien Su | 2023-08-22 |
| 11630786 | Non-sequential page continuous read | — | 2023-04-18 |
| 11550494 | Method to support high reliability multiple times program non-volatile configuration setting | — | 2023-01-10 |
| 11461025 | Data retention in memory devices | E-Yuan Chang | 2022-10-04 |
| 11455254 | Flash memory system and flash memory device thereof | Chun-Lien Su, Chun-Hsiung Hung | 2022-09-27 |
| 11249913 | Continuous read with multiple read commands | Chun-Lien Su | 2022-02-15 |
| 11182302 | Memory device, electronic device, and associated read method | Chun-Lien Su, Chun-Hsiung Hung | 2021-11-23 |
| 11087858 | In-place refresh operation in flash memory | Chun-Lien Su | 2021-08-10 |
| 11049585 | On chip block repair scheme | Chun-Hsiung Hung | 2021-06-29 |
| 11048649 | Non-sequential page continuous read | — | 2021-06-29 |
| 10977121 | Fast page continuous read | Chun-Hsiung Hung | 2021-04-13 |
| 10957384 | Page buffer structure and fast continuous read | Ji-Yu Hung | 2021-03-23 |
| 10643737 | Method for an integrated circuit memory with a status memory for storing repair statuses of row blocks of main column blocks | Chi Lo, Chun-Hsiung Hung | 2020-05-05 |
| 10325662 | Circuit and method for adjusting select gate voltage of non-volatile memory during erasure of memory cells based on a well voltage | Shin-Jang Shen, Wei-Jen Chen | 2019-06-18 |
| 10290364 | Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks | Chi Lo, Chun-Hsiung Hung | 2019-05-14 |
| 9805803 | Circuit for adjusting a select gate voltage of a non-volatile memory during erasure of memory cells based on a well voltage | Shin-Jang Shen, Wei-Jen Chen | 2017-10-31 |