Issued Patents All Time
Showing 1–25 of 96 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12237024 | Memory device and programming method thereof | Kun-Tse Lee, Shih-Chang Huang | 2025-02-25 |
| 11488657 | Fast interval read setup for 3D memory | Jen-Hung Huang | 2022-11-01 |
| 11475954 | Fast interval read setup for 3D NAND flash | Chung-Kuang Chen | 2022-10-18 |
| 11282581 | 3D memory program disturbance improvement | Chien-Fu Huang | 2022-03-22 |
| 10790009 | Sensing a memory device | Chung-Kuang Chen | 2020-09-29 |
| 10650887 | Reading memory cells | Chun-Hsiung Hung, Ming-Chao Lin | 2020-05-12 |
| 10637476 | Clock integrated circuit | Chung-Kuang Chen, Chun-Hsiung Hung | 2020-04-28 |
| 9977627 | Memory device and memory controlling method | Chun-Hsiung Hung, Chung-Kuang Chen | 2018-05-22 |
| 9972383 | Reading memory cells | Chun-Hsiung Hung, Ming-Chao Lin | 2018-05-15 |
| 9887009 | Memory page buffer with simultaneous multiple bit programming capability | Chung-Kuang Chen, Chung-Hsiung Hung | 2018-02-06 |
| 9876502 | Clock integrated circuit | Chung-Kuang Chen, Chun-Hsiung Hung | 2018-01-23 |
| 9679653 | Programming scheme for next starting pulse based on a current program pulse for improving programming speed | Ming-Chao Lin | 2017-06-13 |
| 9589646 | Page buffer circuit having bias voltage application unit and operating method of same | Chung-Kuang Chen, Chun-Hsiung Hung | 2017-03-07 |
| 9570133 | Local word line driver | Chun-Hsiung Hung, Chung-Kuang Chen | 2017-02-14 |
| 9542268 | Dynamic data density ECC | Chung-Kuang Chen, Chun-Hsiung Hung | 2017-01-10 |
| 9536601 | Threshold voltage grouping of memory cells in same threshold voltage range | Chung-Kuang Chen, Chun-Hsiung Hung | 2017-01-03 |
| 9508455 | Memory device and operating method thereof for reducing interference between memory cells | Chung-Kuang Chen, Chun-Hsiung Hung | 2016-11-29 |
| 9471485 | Difference L2P method | Lung-Yi Kuo, Hsin-Yi Ho, Chun-Hsiung Hung | 2016-10-18 |
| 9449666 | Local word line driver | Chung-Kuang Chen, Chun-Hsiung Hung | 2016-09-20 |
| 9437264 | Memory operation latency control | Chun-Hsiung Hung, Ming-Chao Lin | 2016-09-06 |
| 9396770 | Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits | Chung-Kuang Chen, Chun-Hsiung Hung | 2016-07-19 |
| 9349469 | Program verify with multiple sensing | Chung-Kuang Chen, Chun-Hsiung Hung | 2016-05-24 |
| 9281021 | Method and apparatus for reduced read latency for consecutive read operations of memory of an integrated circuit | Chun-Hsiung Hung, Ming-Chao Lin | 2016-03-08 |
| 9270272 | Clock integrated circuit | Chung-Kuang Chen, Chun-Hsiung Hung | 2016-02-23 |
| 9171628 | Incremental step pulse programming (ISPP) scheme capable of determining a next starting pulse based on a current program-verify pulse for improving programming speed | Ming-Chao Lin | 2015-10-27 |