Issued Patents All Time
Showing 1–25 of 221 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426333 | Polysilicon design for replacement gate technology | Harry-Hak-Lay Chuang, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu +1 more | 2025-09-23 |
| 12414361 | Method of manufacturing a semiconductor device | Yi-Sheng Chen, Fu-Jier Fan, Jung-Hui Kao, Yi-Huan Chen, Kau-Chu Lin | 2025-09-09 |
| 12363998 | Recessed gate for an MV device | Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky +2 more | 2025-07-15 |
| 12356658 | Semiconductor structure and method of forming the same | Yi-Huan Chen, Chien-Chih Chou, Szu-Hsien Liu, Huan-Chih Yuan, Jhu-Min Song | 2025-07-08 |
| 12272686 | Semiconductor structure and manufacturing method of the same | Fu-Jier Fan, Alexander Kalnitsky, Jhu-Min Song | 2025-04-08 |
| 12261218 | Semiconductor structure and method of forming the same | Yi-Huan Chen, Chien-Chih Chou, Szu-Hsien Liu | 2025-03-25 |
| 12255207 | Boundary design for high-voltage integration on HKMG technology | Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Ming Chyi Liu, Shih-Chung Hsiao +1 more | 2025-03-18 |
| 12243787 | Method of forming testing module and method for using the same | Jen-Yuan Chang, Jung-Hui Kao | 2025-03-04 |
| 12211926 | Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices | Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky | 2025-01-28 |
| 12191365 | Thicker corner of a gate dielectric structure around a recessed gate electrode for an MV device | Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Szu-Hsien Liu, Huan-Chih Yuan | 2025-01-07 |
| 12176407 | Method of forming a transistor device with a gate structure having a pair of recess regions and a resistive protection layer within | Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Ming-Ta Lei +2 more | 2024-12-24 |
| 12100706 | Semiconductor structure and method of forming thereof | Jhu-Min Song, Chien-Chih Chou, Fu-Jier Fan | 2024-09-24 |
| 12050245 | Semiconductor testing device and method of operating the same | Jung-Hui Kao, Jing Huang, Fu-Hsiung Yang | 2024-07-30 |
| 12021140 | Semiconductor structure and method of forming thereof | Yi-Huan Chen, Chien-Chih Chou, Szu-Hsien Liu, Huan-Chih Yuan, Jhu-Min Song | 2024-06-25 |
| 12002807 | Semiconductor structure | Jing Huang, Ching-En Chen, Jung-Hui Kao | 2024-06-04 |
| 11948938 | Recessed gate for an MV device | Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky +2 more | 2024-04-02 |
| 11862592 | Sidewall spacer to reduce bond pad necking and/or redistribution layer necking | Alexander Kalnitsky | 2024-01-02 |
| 11855091 | Boundary design for high-voltage integration on HKMG technology | Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Ming Chyi Liu, Shih-Chung Hsiao +1 more | 2023-12-26 |
| 11823959 | FUSI gated device formation | Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky +1 more | 2023-11-21 |
| 11810973 | Semiconductor structure and method of forming thereof | Yi-Huan Chen, Chien-Chih Chou, Szu-Hsien Liu | 2023-11-07 |
| 11799007 | Thicker corner of a gate dielectric structure around a recessed gate electrode for an MV device | Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Szu-Hsien Liu, Huan-Chih Yuan | 2023-10-24 |
| 11710712 | Semiconductor device and manufacturing method of the same | Jhu-Min Song, Fu-Jier Fan, Alexander Kalnitsky, Hsiao-Chin Tuan | 2023-07-25 |
| 11705449 | Through silicon via design for stacking integrated circuits | Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu +2 more | 2023-07-18 |
| 11677022 | Semiconductor structure and method of forming thereof | Yi-Huan Chen, Chien-Chih Chou, Szu-Hsien Liu, Huan-Chih Yuan, Jhu-Min Song | 2023-06-13 |
| 11646308 | Through silicon via design for stacking integrated circuits | Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu +2 more | 2023-05-09 |