Issued Patents All Time
Showing 51–75 of 221 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10937785 | Semiconductor device | Yi-Sheng Chen, Fu-Jier Fan, Jung-Hui Kao, Yi-Huan Chen, Kau-Chu Lin | 2021-03-02 |
| 10930776 | High voltage LDMOS transistor and methods for manufacturing the same | Ker Hsiao Huo, Chien-Chih Chou, Yi-Min Chen, Chen-Liang Chu | 2021-02-23 |
| 10916542 | Recessed STI as the gate dielectric of HV device | Yi-Huan Chen, Fu-Jier Fan, Ker Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh +2 more | 2021-02-09 |
| 10879200 | Sidewall spacer to reduce bond pad necking and/or redistribution layer necking | Alexander Kalnitsky | 2020-12-29 |
| 10868141 | Spacer structure and manufacturing method thereof | Fu-Jier Fan, Szu-Hsien Liu | 2020-12-15 |
| 10804220 | Dishing prevention columns for bipolar junction transistors | Yi-Huan Chen, Chien-Chih Chou, Meng-Han Lin | 2020-10-13 |
| 10804093 | Dishing prevention columns for bipolar junction transistors | Yi-Huan Chen, Chien-Chih Chou, Meng-Han Lin | 2020-10-13 |
| 10790387 | High voltage LDMOS transistor and methods for manufacturing the same | Ker Hsiao Huo, Chien-Chih Chou, Yi-Min Chen, Chen-Liang Chu | 2020-09-29 |
| 10790279 | High voltage integration for HKMG technology | Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky +1 more | 2020-09-29 |
| 10748899 | Epitaxial source and drain structures for high voltage devices | Yi-Huan Chen, Chien-Chih Chou | 2020-08-18 |
| 10665510 | Spacer structure and manufacturing method thereof | Alexander Kalnitsky | 2020-05-26 |
| 10658492 | Polysilicon design for replacement gate technology | Harry-Hak-Lay Chuang, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu +1 more | 2020-05-19 |
| 10658318 | Film scheme for bumping | Yao-Wen Chang, Chern-Yow Hsu, Cheng-Yuan Tsai | 2020-05-19 |
| 10629592 | Through silicon via design for stacking integrated circuits | Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu +2 more | 2020-04-21 |
| 10553583 | Boundary region for high-k-metal-gate(HKMG) integration technology | Yi-Huan Chen, Chien-Chih Chou | 2020-02-04 |
| 10535752 | Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices | Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky | 2020-01-14 |
| 10516029 | Dishing prevention dummy structures for semiconductor devices | Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Yi-Sheng Chen +1 more | 2019-12-24 |
| 10510685 | Dishing prevention columns for bipolar junction transistors | Yi-Huan Chen, Chien-Chih Chou, Meng-Han Lin | 2019-12-17 |
| 10510750 | High voltage integration for HKMG technology | Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky +1 more | 2019-12-17 |
| 10403736 | Polysilicon design for replacement gate technology | Harry-Hak-Lay Chuang, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu +1 more | 2019-09-03 |
| 10347757 | Lateral MOSFET | Huei-Ru Liu, Chien-Chih Chou | 2019-07-09 |
| 10340357 | Dishing prevention dummy structures for semiconductor devices | Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Yi-Sheng Chen +1 more | 2019-07-02 |
| 10325964 | OLED merged spacer device | Yi-Huan Chen, Fu-Jier Fan, Ker Hsiao Huo, Li-Hsuan Yeh, Yu Zhao | 2019-06-18 |
| 10297491 | Semiconductor device having isolation structure in well of substrate | Chien-Chih Chou | 2019-05-21 |
| 10164037 | Semiconductor device structure and method for forming the same | Ker Hsiao Huo, Chih-Wen Yao, Fu-Jier Fan, Chen-Liang Chu, Ta-Yuan Kung +4 more | 2018-12-25 |