Issued Patents All Time
Showing 76–100 of 221 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10147814 | Lateral MOSFET | Huei-Ru Liu, Chien-Chih Chou | 2018-12-04 |
| 10096523 | Spacer structure and manufacturing method thereof | Alexander Kalnitsky | 2018-10-09 |
| 10084061 | Polysilicon design for replacement gate technology | Harry-Hak-Lay Chuang, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu +1 more | 2018-09-25 |
| 10050033 | High voltage integration for HKMG technology | Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky +1 more | 2018-08-14 |
| 10014291 | SiC crystalline on Si substrates to allow integration of GaN and Si electronics | Jiun-Lei Jerry Yu, Chun Lin Tsai, Hsiao-Chin Tuan, Alex Kalnitsky | 2018-07-03 |
| 9929251 | Polysilicon design for replacement gate technology | Harry-Hak-Lay Chuang, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu +1 more | 2018-03-27 |
| 9911845 | High voltage LDMOS transistor and methods for manufacturing the same | Ker Hsiao Huo, Chien-Chih Chou, Yi-Min Chen, Chen-Liang Chu | 2018-03-06 |
| 9887302 | Schottky barrier diode | Meng-Han Lin, Chieh-Chih Chou, Chih-Wen Hsiung | 2018-02-06 |
| 9887134 | Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices | Yao-Wen Chang, Jian-Shiou Huang, Cheng-Yuan Tsai | 2018-02-06 |
| 9871105 | Method of forming an isolation structure in a well of a substrate | Chien-Chih Chou | 2018-01-16 |
| 9853149 | Floating grid and crown-shaping poly for improving ILD CMP dishing | Chao-Hsuing Chen, Fu-Jier Fan, Yi-Huan Chen, Ker Hsiao Huo, Szu-Hsien Liu | 2017-12-26 |
| 9691895 | Lateral MOSFET | Huei-Ru Liu, Chien-Chih Chou | 2017-06-27 |
| 9685395 | Wiring layout having differently shaped vias | Harry-Hak-Lay Chuang, Chih-Tsung Yao, Heng-Kai Liu, Ming-Jer Chiu, Chien-Wen Chen | 2017-06-20 |
| 9679988 | Polysilicon design for replacement gate technology | Harry-Hak-Lay Chuang, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu +1 more | 2017-06-13 |
| 9601585 | Transistor having a wing region | Chen-Liang Chu, Fei-Yuh Chen, Yi-Sheng Chen, Shih-Kuang Hsiao, Chun Lin Tsai | 2017-03-21 |
| 9502585 | Schottky barrier diode and method of manufacturing the same | Meng-Han Lin, Chien-Chih Chou, Chih-Wen Hsiung | 2016-11-22 |
| 9455344 | Integrated circuit metal gate structure having tapered profile | Harry-Hak-Lay Chuang, Chiung-Han Yeh, Ming-Yuan Wu, Mong-Song Liang | 2016-09-27 |
| 9437494 | Semiconductor arrangement and formation thereof | Alexander Kalnitsky, Chien-Chih Chou, Chen-Liang Chu, Hsiao-Chin Tuan | 2016-09-06 |
| 9419099 | Method of fabricating spacers in a strained semiconductor device | Chen-Pin Hsu, Harry-Hak-Lay Chuang | 2016-08-16 |
| 9362272 | Lateral MOSFET | Huei-Ru Liu, Chien-Chih Chou | 2016-06-07 |
| 9356108 | Dummy structure for multiple gate dielectric interface and methods | Huei-Ru Liou, Chien-Chih Chou, Gwo-Yuh Shiau | 2016-05-31 |
| 9349655 | Method for mechanical stress enhancement in semiconductor devices | Carlos H. Diaz, Yi-Ming Sheu, Anson Wang, Sheng-Chen Chung, Hao-Yi Tsai +3 more | 2016-05-24 |
| 9318366 | Method of forming integrated circuit having modified isolation structure | Chien-Chih Chou | 2016-04-19 |
| 9299806 | High voltage drain-extended MOSFET having extra drain-OD addition | Yi-Sheng Chen, Chen-Liang Chu, Shih-Kuang Hsiao, Fei-Yuh Chen | 2016-03-29 |
| 9263396 | Photo alignment mark for a gate last process | Chun-Liang Shen, Ming-Yuan Wu, Chiung-Han Yeh, Harry-Hak-Lay Chuang | 2016-02-16 |