Issued Patents All Time
Showing 1–25 of 249 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424256 | Circuit design and layout with high embedded memory density | Fa-Shen Jiang, Hsia-Wei Chen, Hsun-Chung Kuang, Hai-Dang Trinh | 2025-09-23 |
| 12408448 | Deep trench isolation structure and methods for fabrication thereof | Bi-Shen Lee, Chia-Wei Hu, Hai-Dang Trinh, Min-Ying Tsai, Ching-I Li +1 more | 2025-09-02 |
| 12408567 | Memory device structure with data storage element | Hai-Dang Trinh, Hsing-Lien Lin | 2025-09-02 |
| 12364171 | Resistive memory cell with switching layer comprising one or more dopants | Fa-Shen Jiang, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee | 2025-07-15 |
| 12356631 | FeRAM with laminated ferroelectric film and method forming same | Bi-Shen Lee, Yi Yang Wei, Hsing-Lien Lin, Hsun-Chung Kuang, Hai-Dang Trinh | 2025-07-08 |
| 12349366 | Interface film to mitigate size effect of memory device | Bi-Shen Lee, Yi Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang | 2025-07-01 |
| 12340987 | Tunable plasma exclusion zone in semiconductor fabrication | Che-Wei Yang, Chih-Cheng Shih, Sheng-Chan Li, Sheng-Chau Chen | 2025-06-24 |
| 12336201 | Capacitor structure and method of making the same | Jian-Shiou Huang, Chia-Shiung Tsai, Hsing-Lien Lin, Yao-Wen Chang | 2025-06-17 |
| 12293946 | Techniques for wafer stack processing | Yung-Lung Lin, Cheng-Hsien Chou, Kuo-Ming Wu, Hau-Yi Hsiao | 2025-05-06 |
| 12295270 | RRAM device with improved performance | Fa-Shen Jiang, Hai-Dang Trinh, Hsing-Lien Lin, Bi-Shen Lee | 2025-05-06 |
| 12290003 | Conductive structure connection with interconnect structure | Sheng-Chau Chen, Cheng-Tai Hsiao, Hsun-Chung Kuang | 2025-04-29 |
| 12278151 | Semiconductor wafer seal ring having protrusion extending into trench in semiconductor substrate | Ming-Che Lee, Kuo-Ming Wu, Sheng-Chau Chen, Hau-Yi Hsiao, Guanyu Luo +1 more | 2025-04-15 |
| 12272715 | High reflectance isolation structure to increase image sensor performance | Sheng-Chan Li, Hau-Yi Hsiao, Che-Wei Yang, Sheng-Chau Chen | 2025-04-08 |
| 12266579 | Method and system for adjusting the gap between a wafer and a top plate in a thin-film deposition process | Sheng-Chan Li, Sheng-Chau Chen, Cheng-Hsien Chou | 2025-04-01 |
| 12245529 | Diffusion barrier layer in programmable metallization cell | Albert Zhong, Hai-Dang Trinh, Shing-Chyang Pan | 2025-03-04 |
| 12211737 | Cleaning chamber for metal oxide removal | Yen-Liang Lin, Chia-Wen Zhong, Yao-Wen Chang, Min-Chang Ching, Kuo-Liang Lu +1 more | 2025-01-28 |
| 12211741 | Multi-wafer capping layer for metal arcing protection | Chih-Hui Huang, Cheng-Hsien Chou, Kuo-Ming Wu, Sheng-Chan Li | 2025-01-28 |
| 12199120 | Image sensor scheme for optical and electrical improvement | Sheng-Chan Li, Cheng-Hsien Chou, Keng-Yu Chou, Yeur-Luen Tu | 2025-01-14 |
| 12183779 | Integrated circuit and method of forming the same | Ming-Che Lee, Sheng-Chau Chen | 2024-12-31 |
| 12185640 | MRAM MTJ with directly coupled top electrode connection | Sheng-Chau Chen, Cheng-Tai Hsiao, Hsun-Chung Kuang | 2024-12-31 |
| 12160995 | Wakeup free approach to improve the ferroelectricity of FeRAM using a stressor layer | Bi-Shen Lee, Tzu-Yu Lin, Yi Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang | 2024-12-03 |
| 12127483 | Doped sidewall spacer/etch stop layer for memory | Bi-Shen Lee, Hai-Dang Trinh, Hsun-Chung Kuang | 2024-10-22 |
| 12125763 | Trim wall protection method for multi-wafer stacking | Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Kuo-Ming Wu | 2024-10-22 |
| 12102019 | Data storage structure for improving memory cell reliability | Hai-Dang Trinh, Chii-Ming Wu, Tzu-Chung Tsai, Fa-Shen Jiang | 2024-09-24 |
| 12087756 | Protective wafer grooving structure for wafer thinning and methods of using the same | Kuo-Ming Wu, Ming-Che Lee, Hau-Yi Hsiao, Cheng-Hsien Chou, Sheng-Chau Chen | 2024-09-10 |