Issued Patents All Time
Showing 1–25 of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424256 | Circuit design and layout with high embedded memory density | Fa-Shen Jiang, Hsun-Chung Kuang, Hai-Dang Trinh, Cheng-Yuan Tsai | 2025-09-23 |
| 12336442 | Memory device with bottom electrode | Chih-Hung Pan, Chih-Hsiang Chang, Yu-Wen Liao, Wen-Ting Chu | 2025-06-17 |
| 12310036 | Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same | Fa-Shen Jiang, Hai-Dang Trinh, Hsun-Chung Kuang | 2025-05-20 |
| 12232336 | Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same | Fa-Shen Jiang, Hai-Dang Trinh, Hsun-Chung Kuang | 2025-02-18 |
| 12218005 | Integrated circuit device | Fu-Ting Sung, Yu-Wen Liao, Wen-Ting Chu, Fa-Shen Jiang, Tzu-Hsuan Yeh | 2025-02-04 |
| 12075636 | Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same | Fa-Shen Jiang, Hai-Dang Trinh, Hsun-Chung Kuang | 2024-08-27 |
| 11980041 | Method to form memory cells separated by a void-free dielectric structure | Wen-Ting Chu, Yu-Wen Liao | 2024-05-07 |
| 11961545 | Circuit design and layout with high embedded memory density | Fa-Shen Jiang, Hsun-Chung Kuang, Hai-Dang Trinh, Cheng-Yuan Tsai | 2024-04-16 |
| 11894267 | Method for fabricating integrated circuit device | Fu-Ting Sung, Yu-Wen Liao, Wen-Ting Chu, Fa-Shen Jiang, Tzu-Hsuan Yeh | 2024-02-06 |
| 11889705 | Interconnect landing method for RRAM technology | Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu +1 more | 2024-01-30 |
| 11856797 | Resistive switching random access memory with asymmetric source and drain | Chin-Chieh Yang, Chih-Yang Chang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao | 2023-12-26 |
| 11856801 | Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same | Fa-Shen Jiang, Hai-Dang Trinh, Hsun-Chung Kuang | 2023-12-26 |
| 11844286 | Flat bottom electrode via (BEVA) top surface for memory | Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao +3 more | 2023-12-12 |
| 11839090 | Memory cells separated by a void-free dielectric structure | Wen-Ting Chu, Yu-Wen Liao | 2023-12-05 |
| 11751485 | Flat bottom electrode via (BEVA) top surface for memory | Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao +3 more | 2023-09-05 |
| 11723294 | Memory device and method for fabricating the same | Chih-Hung Pan, Chih-Hsiang Chang, Yu-Wen Liao, Wen-Ting Chu | 2023-08-08 |
| 11723292 | RRAM cell structure with laterally offset BEVA/TEVA | Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Chin-Chieh Yang +2 more | 2023-08-08 |
| 11545202 | Circuit design and layout with high embedded memory density | Fa-Shen Jiang, Hsun-Chung Kuang, Hai-Dang Trinh, Cheng-Yuan Tsai | 2023-01-03 |
| 11387411 | Logic compatible RRAM structure and process | Chih-Yang Chang, Chin-Chieh Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao | 2022-07-12 |
| 11315861 | Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory | Wen-Ting Chu, Yu-Wen Liao | 2022-04-26 |
| 11239279 | Resistive switching random access memory with asymmetric source and drain | Chin-Chieh Yang, Chih-Yang Chang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao | 2022-02-01 |
| 11201281 | Method for forming a flat bottom electrode via (BEVA) top surface for memory | Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao +3 more | 2021-12-14 |
| 11094744 | Interconnect landing method for RRAM technology | Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu +1 more | 2021-08-17 |
| 11037990 | Method to form memory cells separated by a void-free dielectric structure | Wen-Ting Chu, Yu-Wen Liao | 2021-06-15 |
| 11037989 | Method to form memory cells separated by a void-free dielectric structure | Wen-Ting Chu, Yu-Wen Liao | 2021-06-15 |