Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12290003 | Conductive structure connection with interconnect structure | Sheng-Chau Chen, Cheng-Yuan Tsai, Hsun-Chung Kuang | 2025-04-29 |
| 12185640 | MRAM MTJ with directly coupled top electrode connection | Sheng-Chau Chen, Cheng-Yuan Tsai, Hsun-Chung Kuang | 2024-12-31 |
| 11594679 | Structure improving reliability of top electrode contact for resistance switching RAM having cells of varying height | Sheng-Chau Chen, Hsun-Chung Kuang | 2023-02-28 |
| 11367623 | Structure and method to expose memory cells with different sizes | Sheng-Chau Chen, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang | 2022-06-21 |
| 11183394 | Structure and method to expose memory cells with different sizes | Sheng-Chau Chen, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang | 2021-11-23 |
| 11183627 | MRAM MTJ top electrode connection | Sheng-Chau Chen, Cheng-Yuan Tsai, Hsun-Chung Kuang | 2021-11-23 |
| 11152426 | Memory device using an etch stop dielectric layer and methods for forming the same | Yen-Chang Chu, Hsun-Chung Kuang | 2021-10-19 |
| 11121315 | Structure improving reliability of top electrode contact for resistance switching RAM having cells of varying height | Sheng-Chau Chen, Hsun-Chung Kuang | 2021-09-14 |
| 10790189 | 3D integrated circuit and methods of forming the same | Hsun-Chung Kuang, Yen-Chang Chu, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu +2 more | 2020-09-29 |
| 10727077 | Structure and method to expose memory cells with different sizes | Sheng-Chau Chen, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang | 2020-07-28 |
| 10529913 | Techniques for MRAM MTJ top electrode connection | Sheng-Chau Chen, Cheng-Yuan Tsai, Hsun-Chung Kuang | 2020-01-07 |
| 10181441 | Through via structure and manufacturing method thereof | Hsun-Chung Kuang | 2019-01-15 |
| 10163651 | Structure and method to expose memory cells with different sizes | Sheng-Chau Chen, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang | 2018-12-25 |
| 10128209 | Wafer bonding process and structure | Ping-Yin Liu, Lan-Lin Chao, Xin-Hua Huang, Hsun-Chung Kuang | 2018-11-13 |
| 10090196 | 3D integrated circuit and methods of forming the same | Hsun-Chung Kuang, Yen-Chang Chu, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu +2 more | 2018-10-02 |
| 9425155 | Wafer bonding process and structure | Ping-Yin Liu, Hsun-Chung Kuang, Xin-Hua Huang, Lan-Lin Chao | 2016-08-23 |
| 9257399 | 3D integrated circuit and methods of forming the same | Hsun-Chung Kuang, Yen-Chang Chu, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu +2 more | 2016-02-09 |
| 9141735 | Circuit device reliability simulation system | Jia-Lin Lo, Ke-Wei Su, Min-Chie Jeng, Feng-Ling Hsiao, Yi-Shun Huang +1 more | 2015-09-22 |
| 8370774 | Constructing mapping between model parameters and electrical parameters | Chen-Ming Tsai, Ke-Wei Su, Min-Chie Jeng, Jia-Lin Lo, Feng-Ling Hsiao +1 more | 2013-02-05 |
| 8275584 | Unified model for process variations in integrated circuits | Chung-Kai Lin, Sally Liu | 2012-09-25 |