Issued Patents All Time
Showing 1–25 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11978712 | Method of forming semiconductor package transmission lines with micro-bump lines | Chin-Wei Kuo, Hsiao-Tsung Yen, Yu-Ling Lin | 2024-05-07 |
| 11410952 | Filter and capacitor using redistribution layer and micro bump layer | Hsiao-Tsung Yen, Jhe-Ching Lu, Yu-Ling Lin, Chin-Wei Kuo | 2022-08-09 |
| 11145767 | Semiconductor structure | Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Chewn-Pu Jou | 2021-10-12 |
| 10971296 | Compact vertical inductors extending in vertical planes | Hsiao-Tsung Yen, Huan-Neng Chen, Yu-Ling Lin, Chin-Wei Kuo, Mei-Show Chen +1 more | 2021-04-06 |
| 10860769 | Method and system for integrated circuit design with on-chip variation and spatial correlation | Katherine H. Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Chen, Ke-Wei Su +2 more | 2020-12-08 |
| 10840201 | Methods and apparatus for transmission lines in packages | Chin-Wei Kuo, Hsiao-Tsung Yen, Yu-Ling Lin | 2020-11-17 |
| 10714441 | Filter and capacitor using redistribution layer and micro bump layer | Hsiao-Tsung Yen, Jhe-Ching Lu, Yu-Ling Lin, Chin-Wei Kuo | 2020-07-14 |
| 10665380 | Compact vertical inductors extending in vertical planes | Hsiao-Tsung Yen, Huan-Neng Chen, Yu-Ling Lin, Chin-Wei Kuo, Mei-Show Chen +1 more | 2020-05-26 |
| 10629756 | Semiconductor structure | Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Chewn-Pu Jou | 2020-04-21 |
| 10521538 | Method and system for integrated circuit design with on-chip variation and spatial correlation | Katherine H. Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Chen, Ke-Wei Su +2 more | 2019-12-31 |
| 10276295 | Compact vertical inductors extending in vertical planes | Hsiao-Tsung Yen, Huan-Neng Chen, Yu-Ling Lin, Chin-Wei Kuo, Mei-Show Chen +1 more | 2019-04-30 |
| 10269746 | Methods and apparatus for transmission lines in packages | Chin-Wei Kuo, Hsiao-Tsung Yen, Yu-Ling Lin | 2019-04-23 |
| 10216879 | Method for establishing aging model of device and analyzing aging state of device with aging model | Yi-Shun Huang, Wai-Kit Lee, Ya-Chin Liang, Cheng Hsiao, Juan Chen +4 more | 2019-02-26 |
| 10019545 | Simulation scheme including self heating effect | Chung-Kai Lin, Ke-Wei Su, Yi-Shun Huang, Ya-Chin Liang, Cheng Hsiao +2 more | 2018-07-10 |
| 9960133 | Filter and capacitor using redistribution layer and micro bump layer | Hsiao-Tsung Yen, Jhe-Ching Lu, Yu-Ling Lin, Chin-Wei Kuo | 2018-05-01 |
| 9923101 | Semiconductor structure | Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Chewn-Pu Jou | 2018-03-20 |
| 9653531 | Methods of manufacturing a package | Hsiao-Tsung Yen, Hsien-Pin Hu, Tzuan-Horng Liu, Chin-Wei Kuo, Chung-Yu Lu +1 more | 2017-05-16 |
| 9633940 | Structure and method for a high-K transformer with capacitive coupling | Hsiao-Tsung Yen, Chin-Wei Kuo, Ho-Hsiang Chen, Yu-Ling Lin | 2017-04-25 |
| 9559053 | Compact vertical inductors extending in vertical planes | Hsiao-Tsung Yen, Huan-Neng Chen, Yu-Ling Lin, Chin-Wei Kuo, Mei-Show Chen +1 more | 2017-01-31 |
| 9530705 | 4 port L-2L de-embedding method | Hsiao-Tsung Yen, Chin-Wei Kuo, Chih-Yuan Chang | 2016-12-27 |
| 9472612 | Integrated capacitor | Chin-Wei Kuo, Cheng-Wei Luo, Hsiao-Tsung Yen, Jun Cheng Huang | 2016-10-18 |
| 9449917 | Method of forming an inductor with magnetic material | Cheng-Wei Luo, Hsiao-Tsung Yen, Chin-Wei Kuo | 2016-09-20 |
| 9449945 | Filter and capacitor using redistribution layer and micro bump layer | Hsiao-Tsung Yen, Jhe-Ching Lu, Yu-Ling Yu, Chin-Wei Kuo | 2016-09-20 |
| 9385246 | Differential MOSCAP device | Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo | 2016-07-05 |
| 9331013 | Integrated capacitor | Hsiao-Tsung Yen, Cheng-Wei Luo, Jun Cheng Huang, Chin-Wei Kuo | 2016-05-03 |