Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12385875 | Biosensor | Wei-Chin Lee, Katherine H. Chiang, Pei-Wen Liu, Kuan-Lun Cheng | 2025-08-12 |
| 12361199 | Integrated circuit layout generation method | Ke-Ying Su, Jon-Hsu Ho, Liang Chen, Wen-Hsing Hsieh, Wen-Koi Lai +4 more | 2025-07-15 |
| 12135930 | Integrated circuit layout generation method and system | Ke-Ying Su, Keng-Hua KUO, Lester Chang | 2024-11-05 |
| 11907636 | Integrated circuit layout generation method | Ke-Ying Su, Jon-Hsu Ho, Liang Chen, Wen-Hsing Hsieh, Wen-Koi Lai +4 more | 2024-02-20 |
| 11842135 | Integrated circuit layout generation method and system | Ke-Ying Su, Keng-Hua KUO, Lester Chang | 2023-12-12 |
| 11392749 | Integrated circuit layout generation method and system | Ke-Ying Su, Jon-Hsu Ho, Liang Chen, Wen-Hsing Hsieh, Wen-Koi Lai +4 more | 2022-07-19 |
| 11293897 | High sensitivity ISFET sensor | Katherine H. Chiang, Jui-Cheng Huang, Tung-Tsun Chen, Wei-Chung Lee, Pei-Wen Liu | 2022-04-05 |
| 11222178 | Text entity extraction method for extracting text from target text based on combination probabilities of segmentation combination of text entities in the target text, apparatus, and device, and storage medium | Hengyao Bao, Yi Chen, Mengliang Rao | 2022-01-11 |
| 11086912 | Automatic questioning and answering processing method and automatic questioning and answering system | Jun Gan, Mengliang Rao | 2021-08-10 |
| 10860769 | Method and system for integrated circuit design with on-chip variation and spatial correlation | Katherine H. Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Chen, Chung-Kai Lin +2 more | 2020-12-08 |
| 10846456 | Integrated circuit modeling methods and systems | Ke-Ying Su, Jon-Hsu Ho, Liang Chen, Wen-Hsing Hsieh, Wen-Koi Lai +4 more | 2020-11-24 |
| 10796059 | Integrated circuit layout generation method and system | Ke-Ying Su, Keng-Hua KUO, Lester Chang | 2020-10-06 |
| 10521538 | Method and system for integrated circuit design with on-chip variation and spatial correlation | Katherine H. Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Chen, Chung-Kai Lin +2 more | 2019-12-31 |
| 10430514 | Method and terminal for extracting webpage content, and non-transitory storage medium | Xinhua Guo, Ning Ma, Jingyao Wang | 2019-10-01 |
| 10216879 | Method for establishing aging model of device and analyzing aging state of device with aging model | Yi-Shun Huang, Wai-Kit Lee, Ya-Chin Liang, Cheng Hsiao, Juan Chen +4 more | 2019-02-26 |
| 10019545 | Simulation scheme including self heating effect | Min-Chie Jeng, Chung-Kai Lin, Yi-Shun Huang, Ya-Chin Liang, Cheng Hsiao +2 more | 2018-07-10 |
| 9904743 | Method for analyzing interconnect process variation | Te-Yu Liu, Cheng Hsiao, Chia-Yi Chen, Wen-Cheng Huang, Ke-Ying Su +1 more | 2018-02-27 |
| 9558314 | Method of designing circuit layout and system for implementing the same | Te-Yu Liu, Ke-Ying Su, Cheng Hsiao, Chia-Yi Chen | 2017-01-31 |
| 9239898 | Circuit simulation with rule check for device | Hsien-Ming Chen, Yi Wang, Jian-Zhi Huang, Chia-Ying Lin, Chia-Chi Ho +2 more | 2016-01-19 |
| 9141735 | Circuit device reliability simulation system | Jia-Lin Lo, Min-Chie Jeng, Feng-Ling Hsiao, Cheng-Tai Hsiao, Yi-Shun Huang +1 more | 2015-09-22 |
| 8370774 | Constructing mapping between model parameters and electrical parameters | Chen-Ming Tsai, Cheng-Tai Hsiao, Min-Chie Jeng, Jia-Lin Lo, Feng-Ling Hsiao +1 more | 2013-02-05 |
| 7421383 | Method for extracting and modeling semiconductor device series resistance and for simulating a semiconductor device with use thereof | Cheng Hsiao, Jaw-Kang Her | 2008-09-02 |
| 7141485 | Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits | Cheng Hsiao, Jaw-Kang Her | 2006-11-28 |
| 6800496 | Characterization methodology for the thin gate oxide device | Chung-Shi Chiang, Chung-Kai Lin, Jaw-Kang Her, Yu-Tai Chia | 2004-10-05 |