Issued Patents All Time
Showing 1–25 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12361199 | Integrated circuit layout generation method | Jon-Hsu Ho, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh, Wen-Koi Lai +4 more | 2025-07-15 |
| 12135930 | Integrated circuit layout generation method and system | Ke-Wei Su, Keng-Hua KUO, Lester Chang | 2024-11-05 |
| 12093629 | Method of manufacturing semiconductor device and system for same | Ze-Ming Wu, Po-Jui Lin | 2024-09-17 |
| 11907636 | Integrated circuit layout generation method | Jon-Hsu Ho, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh, Wen-Koi Lai +4 more | 2024-02-20 |
| 11842135 | Integrated circuit layout generation method and system | Ke-Wei Su, Keng-Hua KUO, Lester Chang | 2023-12-12 |
| 11681847 | Method of manufacturing semiconductor device and system for same | Ze-Ming Wu, Po-Jui Lin | 2023-06-20 |
| 11392749 | Integrated circuit layout generation method and system | Jon-Hsu Ho, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh, Wen-Koi Lai +4 more | 2022-07-19 |
| 10922464 | RC tool accuracy time reduction | Hui-I Wu, Wan-Ting Lo, Niranjan Vepuri, Hsiang-Ho Chang | 2021-02-16 |
| 10846456 | Integrated circuit modeling methods and systems | Jon-Hsu Ho, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh, Wen-Koi Lai +4 more | 2020-11-24 |
| 10796059 | Integrated circuit layout generation method and system | Ke-Wei Su, Keng-Hua KUO, Lester Chang | 2020-10-06 |
| 10515172 | RC tool accuracy time reduction | Hui-I Wu, Wan-Ting Lo, Niranjan Vepuri, Hsiang-Ho Chang | 2019-12-24 |
| 10140407 | Method, device and computer program product for integrated circuit layout generation | Chia-Ming Ho, Adari Rama Bhadra Rao, Meng-Kai Hsu, Kuang-Hung Chang, Wen-Hao Chen +1 more | 2018-11-27 |
| 10019548 | Method of generating modified layout and system therefor | Chia-Ming Ho, Hsien-Hsin Sean Lee | 2018-07-10 |
| 9904743 | Method for analyzing interconnect process variation | Te-Yu Liu, Cheng Hsiao, Chia-Yi Chen, Wen-Cheng Huang, Ke-Wei Su +1 more | 2018-02-27 |
| 9846761 | Mask design based on sensitivities to changes in pattern spacing | Chih-Cheng Chou, Te-Yu Liu, Hsien-Hsin Sean Lee | 2017-12-19 |
| 9710588 | Method of generating modified layout for RC extraction | Chia-Ming Ho, Hsien-Hsin Sean Lee | 2017-07-18 |
| 9558314 | Method of designing circuit layout and system for implementing the same | Te-Yu Liu, Cheng Hsiao, Chia-Yi Chen, Ke-Wei Su | 2017-01-31 |
| 9471738 | Method and apparatus for capacitance extraction | Chih-Cheng Chou, Tsung-Han Wu, Hsien-Hsin Sean Lee, Chung-Hsing Wang | 2016-10-18 |
| 9448467 | Mask shift resistance-inductance method for multiple patterning mask design and a method for performing the same | Chih-Cheng Chou, Te-Yu Liu, Hsien-Hsin Sean Lee | 2016-09-20 |
| 9361423 | RC corner solutions for double patterning technology | Hsiao-Shu Chao, Yi-Kan Cheng | 2016-06-07 |
| 9230052 | Method of generating a simulation model of a predefined fabrication process | Chia-Ming Ho, Hsiao-Shu Chao, Yi-Kan Cheng | 2016-01-05 |
| 9081933 | Methods and apparatus for RC extraction | Te-Yu Liu, Austin Chingyu Chiang, Hsiao-Shu Chao | 2015-07-14 |
| 9021412 | RC extraction methodology for floating silicon substrate with TSV | Ze-Ming Wu, Ching-Shun Yang, Hsiao-Shu Chao | 2015-04-28 |
| 9003345 | Systems and methods for tuning technology files | Meng-Fan Wu, Hsien-Hsin Sean Lee | 2015-04-07 |
| 8954900 | Multi-patterning mask decomposition method and system | Chia-Ming Ho, Kun Ting Tsai, Tsung-Han Wu, Hsien-Hsin Sean Lee | 2015-02-10 |