Issued Patents All Time
Showing 1–25 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12236180 | Integrated circuit and method of manufacturing the same | Yu-Jung Chang, Chin-Chang Hsu, Wen-Ju Yang | 2025-02-25 |
| 12223251 | Standard cell and semiconductor device including anchor nodes | Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Yang | 2025-02-11 |
| 12093176 | Memory circuit and cache circuit configuration | William Wu Shen, Yun-Han Lee | 2024-09-17 |
| 11775724 | Integrated circuit and method of manufacturing the same | Yu-Jung Chang, Chin-Chang Hsu, Wen-Ju Yang | 2023-10-03 |
| 11714946 | Standard cell and semiconductor device including anchor nodes and method of making | Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Yang | 2023-08-01 |
| 11687454 | Memory circuit and cache circuit configuration | William Wu Shen, Yun-Han Lee | 2023-06-27 |
| 11681850 | Multi-patterning graph reduction and checking flow method | Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Yang | 2023-06-20 |
| 11442866 | Computer memory module processing device with cache storage | Liu Ke, Xuan Zhang, Udit Gupta, Carole-Jean Wu, Mark Hempstead +1 more | 2022-09-13 |
| 11216376 | Memory circuit and cache circuit configuration | William Wu Shen, Yun-Han Lee | 2022-01-04 |
| 11138361 | Integrated circuit and system of manufacturing the same | Yu-Jung Chang, Chin-Chang Hsu, Wen-Ju Yang | 2021-10-05 |
| 11106852 | Standard cell and semiconductor device including anchor nodes and method of making | Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Yang | 2021-08-31 |
| 11062075 | Integrated circuit and method for manufacturing same | Yu-Jung Chang, Chin-Chang Hsu, Wen-Ju Yang | 2021-07-13 |
| 11017148 | Multi-patterning graph reduction and checking flow method | Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Yang | 2021-05-25 |
| 10878167 | Method of determining colorability of a semiconductor device and system for implementing the same | Chung-Yun Cheng, Chin-Chang Hsu, Jian-Yi Li, Li Ke, Wen-Ju Yang | 2020-12-29 |
| 10713407 | Standard cell and semiconductor device including anchor nodes | Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Yang | 2020-07-14 |
| 10515185 | Method of determining colorability of a semiconductor device and system for implementing the same | Chung-Yun Cheng, Chin-Chang Hsu, Jian-Yi Li, Li Ke, Wen-Ju Yang | 2019-12-24 |
| 10509883 | Method for layout generation with constrained hypergraph partitioning | Tsun-Yu Yang, Wei Hu, Jui-Feng Kuan, Po-Cheng Pan, Hung-Wen Huang +2 more | 2019-12-17 |
| 10489548 | Integrated circuit and method for manufacturing the same | Yu-Jung Chang, Chin-Chang Hsu, Wen-Ju Yang | 2019-11-26 |
| 10430544 | Multi-patterning graph reduction and checking flow method | Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Yang | 2019-10-01 |
| 10430334 | Memory circuit and cache circuit configuration | William Wu Shen, Yun-Han Lee | 2019-10-01 |
| 10204205 | Method of determining colorability of a semiconductor device and system for implementing the same | Chung-Yun Cheng, Chin-Chang Hsu, Jian-Yi Li, Li Ke, Wen-Ju Yang | 2019-02-12 |
| 10162928 | Method of designing a semiconductor device, system for implementing the method and standard cell | Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Yang | 2018-12-25 |
| 10140407 | Method, device and computer program product for integrated circuit layout generation | Chia-Ming Ho, Adari Rama Bhadra Rao, Meng-Kai Hsu, Kuang-Hung Chang, Ke-Ying Su +1 more | 2018-11-27 |
| 10019548 | Method of generating modified layout and system therefor | Chia-Ming Ho, Ke-Ying Su | 2018-07-10 |
| 9846761 | Mask design based on sensitivities to changes in pattern spacing | Chih-Cheng Chou, Te-Yu Liu, Ke-Ying Su | 2017-12-19 |