Issued Patents All Time
Showing 1–25 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12236180 | Integrated circuit and method of manufacturing the same | Yu-Jung Chang, Hsien-Hsin Sean Lee, Wen-Ju Yang | 2025-02-25 |
| 12223251 | Standard cell and semiconductor device including anchor nodes | Nien-Yu Tsai, Wen-Ju Yang, Hsien-Hsin Sean Lee | 2025-02-11 |
| 11914941 | Integrated circuit layout validation using machine learning | Rachid Salik, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang | 2024-02-27 |
| 11775724 | Integrated circuit and method of manufacturing the same | Yu-Jung Chang, Hsien-Hsin Sean Lee, Wen-Ju Yang | 2023-10-03 |
| 11714946 | Standard cell and semiconductor device including anchor nodes and method of making | Nien-Yu Tsai, Wen-Ju Yang, Hsien-Hsin Sean Lee | 2023-08-01 |
| 11681850 | Multi-patterning graph reduction and checking flow method | Nien-Yu Tsai, Wen-Ju Yang, Hsien-Hsin Sean Lee | 2023-06-20 |
| 11138361 | Integrated circuit and system of manufacturing the same | Yu-Jung Chang, Hsien-Hsin Sean Lee, Wen-Ju Yang | 2021-10-05 |
| 11106852 | Standard cell and semiconductor device including anchor nodes and method of making | Nien-Yu Tsai, Hsien-Hsin Sean Lee, Wen-Ju Yang | 2021-08-31 |
| 11062075 | Integrated circuit and method for manufacturing same | Yu-Jung Chang, Hsien-Hsin Sean Lee, Wen-Ju Yang | 2021-07-13 |
| 11017148 | Multi-patterning graph reduction and checking flow method | Nien-Yu Tsai, Wen-Ju Yang, Hsien-Hsin Sean Lee | 2021-05-25 |
| 11010529 | Integrated circuit layout validation using machine learning | Rachid Salik, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang | 2021-05-18 |
| 10909297 | Deterministic system for device layout optimization | Rachid Salik, Chien-Te Wu | 2021-02-02 |
| 10877370 | Stretchable layout design for EUV defect mitigation | Hsing-Lin Yang, Yen-Hung Lin, Chung-Hsing Wang, Wen-Ju Yang | 2020-12-29 |
| 10878167 | Method of determining colorability of a semiconductor device and system for implementing the same | Chung-Yun Cheng, Hsien-Hsin Sean Lee, Jian-Yi Li, Li Ke, Wen-Ju Yang | 2020-12-29 |
| 10713407 | Standard cell and semiconductor device including anchor nodes | Nien-Yu Tsai, Hsien-Hsin Sean Lee, Wen-Ju Yang | 2020-07-14 |
| 10515185 | Method of determining colorability of a semiconductor device and system for implementing the same | Chung-Yun Cheng, Hsien-Hsin Sean Lee, Jian-Yi Li, Li Ke, Wen-Ju Yang | 2019-12-24 |
| 10489548 | Integrated circuit and method for manufacturing the same | Yu-Jung Chang, Hsien-Hsin Sean Lee, Wen-Ju Yang | 2019-11-26 |
| 10430544 | Multi-patterning graph reduction and checking flow method | Nien-Yu Tsai, Wen-Ju Yang, Hsien-Hsin Sean Lee | 2019-10-01 |
| 10318698 | System and method for assigning color pattern | Yen-Hung Lin, Yuan-Te Hou | 2019-06-11 |
| 10204205 | Method of determining colorability of a semiconductor device and system for implementing the same | Chung-Yun Cheng, Hsien-Hsin Sean Lee, Jian-Yi Li, Li Ke, Wen-Ju Yang | 2019-02-12 |
| 10162928 | Method of designing a semiconductor device, system for implementing the method and standard cell | Nien-Yu Tsai, Hsien-Hsin Sean Lee, Wen-Ju Yang | 2018-12-25 |
| 10121694 | Methods of manufacturing a semiconductor device | Yu-Jung Chang, Ying-Yu Shen, Nien-Yu Tsai, Wen-Ju Yang | 2018-11-06 |
| 10055531 | Layout checking method for advanced double patterning photolithography with multiple spacing criteria | Chung-Hsing Wang, King-Ho Tam, Yuan-Te Hou, Meng-Kai Hsu | 2018-08-21 |
| 10013520 | Method of determining if layout design is N-colorable | Hung-Lung Lin, Chien Lin Ho, Wen-Ju Yang | 2018-07-03 |
| 9659141 | EDA tool and method for conflict detection during multi-patterning lithography | Yen-Hung Lin, Cheng-I Huang, Hung-Lung Lin | 2017-05-23 |