Issued Patents All Time
Showing 1–25 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12402384 | Standard cell design with dummy padding | Sheng-Hsiung Wang, Chun-Yen Lin, Yuan-Te Hou, Tung-Heng Hsieh | 2025-08-26 |
| 12271677 | Timing driven cell swapping | — | 2025-04-08 |
| D1054678 | Sneaker | La Vion Gibson | 2024-12-24 |
| D1050689 | Sandal | La Vion Gibson, William Roth Martin | 2024-11-12 |
| 12131109 | Block level design method for heterogeneous PG-structure cells | Yuan-Te Hou, Chung-Hsing Wang | 2024-10-29 |
| D1039816 | Boot | William Roth Martin, La Vion Gibson, Erin D. Lowenberg | 2024-08-27 |
| 11983475 | Method for manufacturing a cell having pins and semiconductor device based on same | Pin-Dai Sue, Po-Hsiang Huang, Fong-Yuan Chang, Chi-Yu Lu, Sheng-Hsiung Chen +4 more | 2024-05-14 |
| 11853678 | Block level design method for heterogeneous PG-structure cells | Yuan-Te Hou, Chung-Hsing Wang | 2023-12-26 |
| D988647 | Boot | William Roth Martin, La Vion Gibson, Erin D. Lowenberg | 2023-06-13 |
| 11663392 | Timing driven cell swapping | — | 2023-05-30 |
| 11574106 | Method, system, and storage medium of resource planning for designing semiconductor device | Chung-Hsing Wang, Yuan-Te Hou | 2023-02-07 |
| 11574108 | Block level design method for heterogeneous PG-structure cells | Yuan-Te Hou, Chung-Hsing Wang | 2023-02-07 |
| 11574107 | Method for manufacturing a cell having pins and semiconductor device based on same | Pin-Dai Sue, Po-Hsiang Huang, Fong-Yuan Chang, Chi-Yu Lu, Sheng-Hsiung Chen +4 more | 2023-02-07 |
| 11507246 | Method for dynamically showing virtual boundary, electronic device and computer readable storage medium thereof | Ying-Jing Wang | 2022-11-22 |
| D958510 | Boot | William Roth Martin, La Vion Gibson, Erin D. Lowenberg | 2022-07-26 |
| D942744 | Sandal | La Vion Gibson, William Roth Martin | 2022-02-08 |
| 11182527 | Cell placement site optimization | Chung-Hsing Wang, Yuan-Te Hou | 2021-11-23 |
| 11176303 | Constrained cell placement | Chung-Hsing Wang, Yuan-Te Hou | 2021-11-16 |
| 11055466 | Block level design method for heterogeneous PG-structure cells | Yuan-Te Hou, Chung-Hsing Wang | 2021-07-06 |
| 11030372 | Method for generating layout diagram including cell having pin patterns and semiconductor device based on same | Pin-Dai Sue, Chin-Chou Liu, Sheng-Hsiung Chen, Fong-Yuan Chang, Lee-Chung Lu +4 more | 2021-06-08 |
| 11029753 | Human computer interaction system and human computer interaction method | Chieh-Kai Wang, Shih-Hao Ke, Wei-Chi Yen | 2021-06-08 |
| 10990741 | Multiple patterning method and system for implementing the method | Chung-Hsing Wang, Yuan-Te Hou | 2021-04-27 |
| 10977416 | Timing driven cell swapping | — | 2021-04-13 |
| 10956643 | Method, system, and storage medium of resource planning for designing semiconductor device | Chung-Hsing Wang, Yuan-Te Hou | 2021-03-23 |
| 10877370 | Stretchable layout design for EUV defect mitigation | Hsing-Lin Yang, Chin-Chang Hsu, Chung-Hsing Wang, Wen-Ju Yang | 2020-12-29 |