Issued Patents All Time
Showing 1–25 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426380 | Integrated circuit having angled conductive feature | Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien | 2025-09-23 |
| 12402384 | Standard cell design with dummy padding | Chun-Yen Lin, Yen-Hung Lin, Yuan-Te Hou, Tung-Heng Hsieh | 2025-08-26 |
| 12376338 | Semiconductor device structure with dielectric dummy gate and method for forming the same | Tung-Heng Hsieh | 2025-07-29 |
| 12211787 | Interconnect structures and methods of fabrication thereof | Chao-Hsun Wang, Wang-Jung Hsueh, Fu-Kai Yang, Mei-Yun Wang, Shih-Hsien Huang | 2025-01-28 |
| 12199034 | Via rail structure | Hao Kuang, Tung-Heng Hsieh, Bao-Ru Young, Wang-Jung Hsueh, Pang-Chi Wu | 2025-01-14 |
| 11996329 | Method and IC design with non-linear power rails | Bao-Ru Young, Tung-Heng Hsieh | 2024-05-28 |
| 11675949 | Space optimization between SRAM cells and standard cells | Feng-Ming Chang, Ruey-Wen Chang, Ping-Wei Wang, Chi-Yu Lu | 2023-06-13 |
| 11640936 | Interconnect structures and methods of fabrication thereof | Chao-Hsun Wang, Wang-Jung Hsueh, Fu-Kai Yang, Mei-Yun Wang, Shih-Hsien Huang | 2023-05-02 |
| 11631661 | Integrated circuit having angled conductive feature | Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien | 2023-04-18 |
| 11581221 | Method and IC design with non-linear power rails | Tung-Heng Hsieh, Bao-Ru Young | 2023-02-14 |
| 11495494 | Methods for reducing contact depth variation in semiconductor fabrication | Yun Lee, Chen-Ming Lee, Fu-Kai Yang, Yi-Jyun Huang, Mei-Yun Wang | 2022-11-08 |
| 11281835 | Cell layout and structure | Tung-Heng Hsieh, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu +2 more | 2022-03-22 |
| 11177382 | FinFET having a relaxation prevention anchor and related methods | Yung Feng Chang, Tung-Heng Hsieh | 2021-11-16 |
| 11075164 | Semiconductor device including a conductive feature over an active region | Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien | 2021-07-27 |
| 11062945 | Methods for reducing contact depth variation in semiconductor fabrication | Yun Lee, Chen-Ming Lee, Fu-Kai Yang, Yi-Jyun Huang, Mei-Yun Wang | 2021-07-13 |
| 11031334 | Semiconductor device including a conductive feature over an active region | Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien | 2021-06-08 |
| 11024622 | Integrated circuit having angled conductive feature | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Ting-Wei Chiang, Li-Chun Tien | 2021-06-01 |
| 10854512 | Method and IC design with non-linear power rails | Tung-Heng Hsieh, Bao-Ru Young | 2020-12-01 |
| 10685880 | Methods for reducing contact depth variation in semiconductor fabrication | Yun Lee, Chen-Ming Lee, Fu-Kai Yang, Yi-Jyun Huang, Mei-Yun Wang | 2020-06-16 |
| 10664639 | Cell layout and structure | Tung-Heng Hsieh, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu +2 more | 2020-05-26 |
| 10522681 | Method of forming a FinFET having a relaxation prevention anchor | Yung Feng Chang, Tung-Heng Hsieh | 2019-12-31 |
| 10522527 | System and method of processing cutting layout and example switching circuit | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Ting-Wei Chiang, Li-Chun Tien | 2019-12-31 |
| 10515850 | Method and IC design with non-linear power rails | Tung-Heng Hsieh, Bao-Ru Young | 2019-12-24 |
| 10504837 | Semiconductor device including a conductive feature over an active region | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Ting-Wei Chiang, Li-Chun Tien | 2019-12-10 |
| 10276718 | FinFET having a relaxation prevention anchor | Yung Feng Chang, Tung-Heng Hsieh | 2019-04-30 |