Issued Patents All Time
Showing 1–25 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12402384 | Standard cell design with dummy padding | Sheng-Hsiung Wang, Chun-Yen Lin, Yen-Hung Lin, Tung-Heng Hsieh | 2025-08-26 |
| 12229489 | System and method of verifying slanted layout components | Min-Yuan Tsai | 2025-02-18 |
| 12131109 | Block level design method for heterogeneous PG-structure cells | Yen-Hung Lin, Chung-Hsing Wang | 2024-10-29 |
| 12008302 | Integrated circuit with thicker metal lines on lower metallization layer | Kuang-Hung Chang, Chung-Hsing Wang, Yung-Chin Hou | 2024-06-11 |
| 11861288 | System and method of verifying slanted layout components | Min-Yuan Tsai | 2024-01-02 |
| 11853678 | Block level design method for heterogeneous PG-structure cells | Yen-Hung Lin, Chung-Hsing Wang | 2023-12-26 |
| 11720738 | Leakage analysis on semiconductor device | Cheng-Hua Liu, Yun-Xiang Lin, Chung-Hsing Wang | 2023-08-08 |
| 11714949 | Leakage analysis on semiconductor device | Cheng-Hua Liu, Yun-Xiang Lin, Chung-Hsing Wang | 2023-08-01 |
| 11593546 | Integrated circuit with thicker metal lines on lower metallization layer | Kuang-Hung Chang, Chung-Hsing Wang, Yung-Chin Hou | 2023-02-28 |
| 11574108 | Block level design method for heterogeneous PG-structure cells | Yen-Hung Lin, Chung-Hsing Wang | 2023-02-07 |
| 11574106 | Method, system, and storage medium of resource planning for designing semiconductor device | Yen-Hung Lin, Chung-Hsing Wang | 2023-02-07 |
| 11294286 | Pattern formation method using a photo mask for manufacturing a semiconductor device | Ru-Gun Liu, Chin-Hsiang Lin, Cheng-I Huang, Chih-Ming Lai, Chien-Wen Lai +2 more | 2022-04-05 |
| 11182527 | Cell placement site optimization | Yen-Hung Lin, Chung-Hsing Wang | 2021-11-23 |
| 11176303 | Constrained cell placement | Yen-Hung Lin, Chung-Hsing Wang | 2021-11-16 |
| 11113443 | Integrated circuit with thicker metal lines on lower metallization layer | Kuang-Hung Chang, Chung-Hsing Wang, Yung-Chin Hou | 2021-09-07 |
| 11055466 | Block level design method for heterogeneous PG-structure cells | Yen-Hung Lin, Chung-Hsing Wang | 2021-07-06 |
| 11030381 | Leakage analysis on semiconductor device | Cheng-Hua Liu, Yun-Xiang Lin, Chung-Hsing Wang | 2021-06-08 |
| 10990741 | Multiple patterning method and system for implementing the method | Yen-Hung Lin, Chung-Hsing Wang | 2021-04-27 |
| 10956643 | Method, system, and storage medium of resource planning for designing semiconductor device | Yen-Hung Lin, Chung-Hsing Wang | 2021-03-23 |
| 10943046 | Semiconductor apparatus including uncrowned and crowned cells and method of making | Prasenjit Ray, Lee-Chung Lu, Meng-Kai Hsu, Wen-Hao Chen | 2021-03-09 |
| 10878157 | Variant cell height integrated circuit design | Yen-Hung Lin, Chung-Hsing Wang | 2020-12-29 |
| 10671788 | Method, system, and storage medium of resource planning for designing semiconductor device | Yen-Hung Lin, Chung-Hsing Wang | 2020-06-02 |
| 10643017 | Rule checking for multiple patterning technology | Meng-Kai Hsu, Wen-Hao Chen | 2020-05-05 |
| 10642949 | Cell placement site optimization | Yen-Hung Lin, Chung-Hsing Wang | 2020-05-05 |
| 10565341 | Constrained cell placement | Yen-Hung Lin, Chung-Hsing Wang | 2020-02-18 |