Issued Patents All Time
Showing 26–50 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515175 | Block-level design method for heterogeneous PG-structure cells | Yen-Hung Lin, Chung-Hsing Wang | 2019-12-24 |
| 10489547 | Multiple patterning method, system for implementing the method and layout formed | Yen-Hung Lin, Chung-Hsing Wang | 2019-11-26 |
| 10452805 | Method of reconfiguring uncrowned standard cells and semiconductor apparatus including uncrowned and crowned cells | Prasenjit Ray, Lee-Chung Lu, Meng-Kai Hsu, Wen-Hao Chen | 2019-10-22 |
| 10318698 | System and method for assigning color pattern | Yen-Hung Lin, Chin-Chang Hsu | 2019-06-11 |
| 10177097 | Multiple driver pin integrated circuit structure | Chih-Yeh Yu, Wen-Hao Chen | 2019-01-08 |
| 10169520 | Method of reconfiguring uncrowned standard cells and semiconductor apparatus including uncrowned and crowned cells | Prasenjit Ray, Lee-Chung Lu, Meng-Kai Hsu, Wen-Hao Chen | 2019-01-01 |
| 10162929 | Systems and methods for using multiple libraries with different cell pre-coloring | Meng-Kai Hsu, Wen-Hao Chen | 2018-12-25 |
| 10089433 | Method for triple-patterning friendly placement | Meng-Kai Hsu, Wen-Hao Chen | 2018-10-02 |
| 10055531 | Layout checking method for advanced double patterning photolithography with multiple spacing criteria | Chung-Hsing Wang, King-Ho Tam, Chin-Chang Hsu, Meng-Kai Hsu | 2018-08-21 |
| 10050028 | Semiconductor device with reduced leakage current | Shih-Wei Peng, Chung-Hsing Wang, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng +1 more | 2018-08-14 |
| 9971863 | Rule checking for multiple patterning technology | Meng-Kai Hsu, Wen-Hao Chen | 2018-05-15 |
| 9935057 | Multiple driver pin integrated circuit structure | Chih-Yeh Yu, Wen-Hao Chen | 2018-04-03 |
| 9799602 | Integrated circuit having a staggered fishbone power network | Kuang-Hung Chang, Wen-Hao Chen, Kumar Lalgudi | 2017-10-24 |
| 9768119 | Apparatus and method for mitigating dynamic IR voltage drop and electromigration affects | Chih-Yeh Yu, Chung-Min Fu, Wen-Hao Chen, Wan-Yu Lo | 2017-09-19 |
| 9754073 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2017-09-05 |
| 9747402 | Methods for double-patterning-compliant standard cell design | Huang-Yu Chen, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang, Yi-Kan Cheng +2 more | 2017-08-29 |
| 9659133 | Method, system and computer program product for generating layout for semiconductor device | Yen-Hung Lin, Chi Wei Hu, Chung-Hsing Wang, Chin-Chou Liu | 2017-05-23 |
| 9627310 | Semiconductor device with self-aligned interconnects | Shih-Ming Chang, Ken-Hsien Hsieh, Tsong-Hua Ou, Ru-Gun Liu, Fang-Yu Fan | 2017-04-18 |
| 9558312 | Electromigration resistant standard cell device | Lee-Chung Lu, Wen-Hao Chen, Shen-Feng Chen, Meng-Fu You | 2017-01-31 |
| 9553043 | Interconnect structure having smaller transition layer via | Lee-Chung Lu, Wen-Hao Chen, Fang-Yu Fan, Yu-Hsiang Kao, Dian-Hau Chen +2 more | 2017-01-24 |
| 9543193 | Non-hierarchical metal layers for integrated circuits | Lee-Chung Lu, Shyue-Shyh Lin, Li-Chun Tien, Dian-Hau Chen | 2017-01-10 |
| 9436793 | Tier based layer promotion and demotion | Yen-Hung Lin, Chi Wei Hu, Chung-Hsing Wang, Chin-Chou Liu | 2016-09-06 |
| 9418196 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2016-08-16 |
| 9405880 | Semiconductor arrangement formation | Yen-Hung Lin, Chi Wei Hu, Chung-Hsing Wang, Chin-Chou Liu | 2016-08-02 |
| 9317650 | Double patterning technology (DPT) layout routing | Huang-Yu Chen, Fang-Yu Fan, Wen-Hao Chen, Chung-Hsing Wang, Yi-Kan Cheng | 2016-04-19 |