Issued Patents All Time
Showing 1–25 of 261 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431428 | Integrated circuits and methods for power delivery | Ming Chian Tsai, Shih-Wei Peng, Wei-Cheng Lin | 2025-09-30 |
| 12426323 | Semiconductor device including vertical transistor with back side power structure | Shih-Wei Peng, Te-Hsin Chiu | 2025-09-23 |
| 12414344 | Semiconductor device having active regions of different dimensions and method of manufacturing the same | Ching-Yu Huang, Wei-Cheng TZENG, Wei-Cheng Lin | 2025-09-09 |
| 12402415 | Integrated circuit with backside power rail and backside interconnect | Shih-Wei Peng, Guo-Huei Wu | 2025-08-26 |
| 12400964 | Integrated circuit | Shih-Wei Peng, Chia-Tien Wu | 2025-08-26 |
| 12396255 | Multiple back side/buried power rail (BPR) cell including field-effect transistors with air void between two adjacent BPR cells | Te-Hsin Chiu, Kam-Tou Sio | 2025-08-19 |
| 12388428 | Integrated circuit having latch with transistors of different gate widths | Ching-Yu Huang, Wei-Cheng Lin | 2025-08-12 |
| 12388016 | Deep lines and shallow lines in signal conducting paths | Wei-An Lai, Te-Hsin Chiu, Shih-Wei Peng, Wei-Cheng Lin, Chia-Tien Wu | 2025-08-12 |
| 12388013 | Three dimensional integrated circuit with monolithic inter-tier vias (MIV) | Shih-Wei Peng, Kam-Tou Sio, Wei-Cheng Lin, Wei-An Lai | 2025-08-12 |
| 12367332 | Mixed poly pitch design solution for power trim | Shih-Wei Peng, Lipen Yuan, Wei-Cheng Lin | 2025-07-22 |
| 12368106 | Diagonal vias in semiconductor structures | Shih-Wei Peng, Chia-Tien Wu | 2025-07-22 |
| 12341098 | Metal patterning for internal cell routing | Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Wei-Cheng Lin | 2025-06-24 |
| 12339321 | Semiconductor device and method of failure analysis for semiconductor device | Shih-Wei Peng, Wei-Cheng Lin | 2025-06-24 |
| 12336296 | Semiconductor device including source/drain contact having height below gate stack | Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Shun Li Chen, Kam-Tou Sio +3 more | 2025-06-17 |
| 12334179 | Cell structures and power routing for integrated circuits | Shih-Wei Peng, Kam-Tou Sio | 2025-06-17 |
| 12327786 | Decoupling capacitors with back side power rails | Kam-Tou Sio | 2025-06-10 |
| 12321679 | Integrated circuit, system and method of forming the same | Shih-Wei Peng, Te-Hsin Chiu | 2025-06-03 |
| 12324245 | Layout architecture for a cell | Shi-Wei Peng, Hui-Zhong Zhuang, Wei-Cheng Lin, Guo-Huei Wu | 2025-06-03 |
| 12324228 | Methods of resistance and capacitance reduction to circuit output nodes | Po-Chia Lai, Shang-Wei Fang, Meng-Hung Shen, Ting-Wei Chiang, Jung-Chan Yang +1 more | 2025-06-03 |
| 12315804 | Back side signal routing in a circuit with a relay cell | Shih-Wei Peng, Wei-Cheng Lin | 2025-05-27 |
| 12314650 | Integrated circuit device and manufacturing method of the same | Ching-Yu Huang, Wei-Cheng TZENG, Shih-Wei Peng, Wei-Cheng Lin | 2025-05-27 |
| 12307183 | Variable width nano-sheet field-effect transistor cell structure | Wei-An Lai, Wei-Cheng Lin, Yan-Hao Chen, Lipen Yuan, Hui-Zhong Zhuang +1 more | 2025-05-20 |
| 12300623 | Integrated circuit | Shih-Wei Peng, Chia-Tien Wu | 2025-05-13 |
| 12300609 | Two-dimensional (2D) metal structure and method of forming the same | Shih-Wei Peng, Ken-Hsien Hsieh | 2025-05-13 |
| 12300608 | Method of manufacturing semiconductor device | Shih-Wei Peng, Hui-Ting Yang, Wei-Cheng Lin | 2025-05-13 |