Issued Patents All Time
Showing 26–50 of 261 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12300609 | Two-dimensional (2D) metal structure and method of forming the same | Shih-Wei Peng, Ken-Hsien Hsieh | 2025-05-13 |
| 12288785 | Layout designs of integrated circuits having backside routing tracks | Wei-An Lai, Shih-Wei Peng, Wei-Cheng Lin | 2025-04-29 |
| 12283477 | Method of manufacturing a semiconductor device | Shih-Wei Peng, Chia-Tien Wu | 2025-04-22 |
| 12283546 | Integrated circuit and method for forming the same | Shih-Wei Peng, Wei-Cheng Lin, Cheng-Chi Chuang | 2025-04-22 |
| 12278185 | Power distribution method | Shih-Wei Peng, Te-Hsin Chiu | 2025-04-15 |
| 12278238 | Semiconductor structure and method of forming the same | Shih-Wei Peng, Te-Hsin Chiu, Wei-Cheng Lin | 2025-04-15 |
| 12266657 | Hybrid cell-based device, layout, and method | Yu-Xuan Huang, Shih-Wei Peng, Te-Hsin Chiu, Hou-Yu Chen, Kuan-Lun Cheng | 2025-04-01 |
| 12265775 | Semiconductor device with reduced power | Shih-Wei Peng, Ching-Yu Huang | 2025-04-01 |
| 12261116 | Backside signal routing | Ching-Yu Huang, Wei-Cheng Lin, Shih-Wei Peng, Yi-Kan Cheng | 2025-03-25 |
| 12261167 | Structure and method of power supply routing in semiconductor device | Shih-Wei Peng | 2025-03-25 |
| 12261113 | Middle-end-of-line strap for standard cell | Meng-Hung Shen, Chih-Liang Chen, Charles Chew-Yuen Young, Kam-Tou Sio, Wei-Cheng Lin | 2025-03-25 |
| 12261115 | Semiconductor devices and methods of manufacturing thereof | Kam-Tou Sio | 2025-03-25 |
| 12255148 | Power distribution structure and method | Shih-Wei Peng, Te-Hsin Chiu | 2025-03-18 |
| 12255203 | Monolithic three dimensional integrated circuit | Kam-Tou Sio, Shih-Wei Peng | 2025-03-18 |
| 12255238 | Integrated circuit, system and method of forming same | Shih-Wei Peng, Chih-Min HSIAO | 2025-03-18 |
| 12237334 | Semiconductor structure | Shih-Wei Peng, Wei-Cheng Lin | 2025-02-25 |
| 12230572 | Backside signal interconnection | Yu-Xuan Huang, Ching-Wei Tsai, Yi-Hsun Chiu, Yi-Bo Liao, Kuan-Lun Cheng +6 more | 2025-02-18 |
| 12230624 | Integrated circuit with mixed row heights | Kam-Tou Sio, Chung-Hsing Wang, Yi-Kan Cheng | 2025-02-18 |
| 12218050 | Manufacturing method for semiconductor device | Te-Hsin Chiu, Wei-An Lai, Meng-Hung Shen, Wei-Cheng Lin, Kam-Tou Sio | 2025-02-04 |
| 12218057 | Integrated circuit with backside interconnections and method of making same | Shih-Wei Peng, Te-Hsin Chiu, Wei-An Lai, Ching-Wei Tsai | 2025-02-04 |
| 12218141 | Hybrid fin field-effect transistor cell structures and related methods | Wei-An Lai, Hui-Zhong Zhuang, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen | 2025-02-04 |
| 12204838 | Structure and method for tying off dummy gate in semiconductor device | Shih-Wei Peng, Meng-Hung Shen, Wei-An Lai | 2025-01-21 |
| 12183788 | Semiconductor arrangement comprising a source pad, gate pad, drain pad, backside interconnect line, and backside contact, and backside conductive line and method of making | Shih-Wei Peng | 2024-12-31 |
| 12170277 | Integrated circuit and manufacturing method of the same | Kam-Tou Sio | 2024-12-17 |
| 12148700 | Semiconductor device, and associated method and system | Shih-Wei Peng, Wei-Cheng Lin | 2024-11-19 |