Issued Patents All Time
Showing 1–25 of 201 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12433032 | Semiconductor structure including boundary header cell and method for manufacturing the same | Hao-Tien Kan, Yan You, Chin-Shen Lin, Kuo-Nan Yang | 2025-09-30 |
| 12380265 | Integrated circuit and method of forming the same | John Lin, Chin-Shen Lin, Kuo-Nan Yang | 2025-08-05 |
| 12353816 | Structure and method of rectangular cell in semiconductor device | Pochun Wang, Jerry Chang Jui Kao, Jung-Chan Yang, Hui-Zhong Zhuang, Tzu-Ying Lin | 2025-07-08 |
| 12346285 | Diagonal torus network | Jerry Chang Jui Kao, Huang-Yu Chen, Yung-Chen Chien, Tzu-Ying Lin, Wei-Hsiang Ma | 2025-07-01 |
| 12336295 | Integrated circuit device and method | Wei-Ren Chen, Cheng-Yu Lin, Hui-Zhong Zhuang, Yung-Chen Chien, Jerry Chang Jui Kao +1 more | 2025-06-17 |
| 12254260 | Systems and methods for integrated circuit layout | Sheng-Hsiung Chen, Chun-Chen Chen, Shao-Huan Wang, Kuo-Nan Yang, Ren-Zheng Liao +1 more | 2025-03-18 |
| 12243821 | Conductive line structures and method of forming same | Hiranmay Biswas, Chi-Yeh Yu, Kuo-Nan Yang, Stefan Rusu, Chin-Shen Lin | 2025-03-04 |
| 12230624 | Integrated circuit with mixed row heights | Kam-Tou Sio, Jiann-Tyng Tzeng, Yi-Kan Cheng | 2025-02-18 |
| 12191248 | Semiconductor arrangement and method of making | Wan-Yu Lo, Chin-Shen Lin, Kuo-Nan Yang, Hsiang-Ku Shen, Dian-Hau Chen | 2025-01-07 |
| 12182488 | Semiconductor device including standard-cell-adapted power grid arrangement | Hiranmay Biswas, Chin-Shen Lin, Kuo-Nan Yang | 2024-12-31 |
| 12176288 | Semiconductor device including frontside power mesh and backside power mesh and manufacturing method thereof | Wan-Yu Lo, Chin-Shen Lin, Chi-Yu Lu, Kuo-Nan Yang, Chih-Liang Chen | 2024-12-24 |
| 12175180 | Systems and methods for context aware circuit design | Li-Chung Hsu, Yen-Pin Chen, Sung-Yen Yeh, Jerry Chang Jui Kao | 2024-12-24 |
| 12131109 | Block level design method for heterogeneous PG-structure cells | Yen-Hung Lin, Yuan-Te Hou | 2024-10-29 |
| 12112117 | Method of manufacturing a semiconductor device including PG-aligned cells | Hiranmay Biswas, Kuo-Nan Yang | 2024-10-08 |
| 12107048 | Layouts for conductive layers in integrated circuits | Wan-Yu Lo, Chin-Shen Lin, Kuo-Nan Yang, Meng-Xiang Lee, Hao-Tien Kan +1 more | 2024-10-01 |
| 12106030 | Method of forming merged pillar structures and method of generating layout diagram of same | Hiranmay Biswas, Kuo-Nan Yang, Yi-Kan Cheng | 2024-10-01 |
| 12093625 | Integrated circuit design method, system and computer program product | Wan-Yu Lo, Kuo-Nan Yang, Chin-Shen Lin | 2024-09-17 |
| 12087690 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Fong-Yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang +6 more | 2024-09-10 |
| 12086522 | Method of generating netlist including proximity-effect-inducer (PEI) parameters | Yen-Pin Chen, Florentin Dartu, Wei-Chih Hsieh, Tzu-Hen Lin | 2024-09-10 |
| 12067337 | Power grid, IC and method for placing power grid | Hiranmay Biswas, Kuo-Nan Yang | 2024-08-20 |
| 12039242 | Structure and method of non-rectangular cell in semiconductor device | Pochun Wang, Jerry Chang Jui Kao, Jung-Chan Yang, Hui-Zhong Zhuang, Tzu-Ying Lin | 2024-07-16 |
| 12019972 | Method and system of forming semiconductor device | Kuo-Nan Yang, Wan-Yu Lo, Hiranmay Biswas | 2024-06-25 |
| 12008302 | Integrated circuit with thicker metal lines on lower metallization layer | Kuang-Hung Chang, Yuan-Te Hou, Yung-Chin Hou | 2024-06-11 |
| 11943939 | Integrated circuit device and method | Meng-Kai Hsu, Jerry Chang Jui Kao, Chin-Shen Lin, Ming-Tao Yu, Tzu-Ying Lin | 2024-03-26 |
| 11942469 | Backside conducting lines in integrated circuits | Wei-An Lai, Shih-Wei Peng, Te-Hsin Chiu, Jiann-Tyng Tzeng | 2024-03-26 |