Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12369389 | Integrated circuit in hybrid row height structure | Jerry Chang Jui Kao, Hui-Zhong Zhuang, Sung-Yen Yeh, Yung-Chen Chien, Jung-Chan Yang +1 more | 2025-07-22 |
| 12210811 | Layout context-based cell timing characterization | Zhe-Wei Jiang, Jerry Chang Jui Kao, Sung-Yen Yeh | 2025-01-28 |
| 12175180 | Systems and methods for context aware circuit design | Yen-Pin Chen, Sung-Yen Yeh, Jerry Chang Jui Kao, Chung-Hsing Wang | 2024-12-24 |
| 12074069 | Semiconductor device and integrated circuit in hybrid row height structure | Jerry Chang Jui Kao, Hui-Zhong Zhuang, Sung-Yen Yeh, Yung-Chen Chien, Jung-Chan Yang +1 more | 2024-08-27 |
| 11853676 | Layout context-based cell timing characterization | Zhe-Wei Jiang, Jerry Chang Jui Kao, Sung-Yen Yeh | 2023-12-26 |
| 11816413 | Systems and methods for context aware circuit design | Yen-Pin Chen, Sung-Yen Yeh, Jerry Chang Jui Kao, Chung-Hsing Wang | 2023-11-14 |
| 11791213 | Integrated circuit in hybrid row height structure | Jerry Chang Jui Kao, Hui-Zhong Zhuang, Sung-Yen Yeh, Yung-Chen Chien, Jung-Chan Yang +1 more | 2023-10-17 |
| 11783106 | Circuit testing and manufacture using multiple timing libraries | Ravi Babu Pittu, Chung-Hsing Wang, Sung-Yen Yeh | 2023-10-10 |
| 11531802 | Layout context-based cell timing characterization | Zhe-Wei Jiang, Jerry Chang Jui Kao, Sung-Yen Yeh | 2022-12-20 |
| 11355395 | Integrated circuit in hybrid row height structure | Jerry Chang Jui Kao, Hui-Zhong Zhuang, Sung-Yen Yeh, Yung-Chen Chien, Jung-Chan Yang +1 more | 2022-06-07 |
| 11068637 | Systems and methods for context aware circuit design | Yen-Pin Chen, Sung-Yen Yeh, Jerry Chang Jui Kao, Chung-Hsing Wang | 2021-07-20 |
| 11003820 | Method of determining a worst case in timing analysis | Ravi Babu Pittu, Sung-Yen Yeh, Chung-Hsing Wang | 2021-05-11 |
| 10977402 | Circuit testing and manufacture using multiple timing libraries | Ravi Babu Pittu, Chung-Hsing Wang, Sung-Yen Yeh | 2021-04-13 |
| 10785685 | Cloud radio access network system and control method thereof | Chih-Wei Chao, Yu-Hsin Kuo, Po-Wei Shih, Shih-Chi Lee | 2020-09-22 |
| 10776545 | Method of determing a worst case in timing analysis | Ravi Babu Pittu, Sung-Yen Yeh, Chung-Hsing Wang | 2020-09-15 |
| 10747924 | Method for manufacturing integrated circuit with aid of pattern based timing database indicating aging effect | Ravi Babu Pittu, Sung-Yen Yeh, Chung-Hsing Wang | 2020-08-18 |
| 10567970 | Cloud radio access network system and control method thereof | Chih-Wei Chao, Yu-Hsin Kuo, Po-Wei Shih, Shih-Chi Lee | 2020-02-18 |
| 10503849 | Circuit testing and manufacture using multiple timing libraries | Ravi Babu Pittu, Chung-Hsing Wang, Sung-Yen Yeh | 2019-12-10 |
| 10216879 | Method for establishing aging model of device and analyzing aging state of device with aging model | Yi-Shun Huang, Wai-Kit Lee, Ya-Chin Liang, Cheng Hsiao, Juan Chen +4 more | 2019-02-26 |
| 10176284 | Semiconductor circuit design and manufacture method | Tai-Yu Cheng, Sung-Yen Yeh, King-Ho Tam, Yen-Pin Chen, Chung-Hsing Wang | 2019-01-08 |
| 9400866 | Layout modification method and system | Meng-Xiang Lee, Shih-Hsien Yang, Ho Che Yu, King-Ho Tam, Chung-Hsing Wang | 2016-07-26 |
| 9311440 | System and method of electromigration avoidance for automatic place-and-route | Jerry Chang Jui Kao, King-Ho Tam, Meng-Xiang Lee, Chi-Yeh Yu, Chung-Min Fu +1 more | 2016-04-12 |
| 9122839 | Layout modification method and system | Meng-Xiang Lee, Shih-Hsien Yang, Ho Che Yu, King-Ho Tam, Chung-Hsing Wang | 2015-09-01 |
| 8826195 | Layout modification method and system | Meng-Xiang Lee, Shih-Hsien Yang, Ho Che Yu, King-Ho Tam, Chung-Hsing Wang | 2014-09-02 |
| 7967401 | Systemic cabinet | — | 2011-06-28 |