Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367333 | Automated system and method for circuit design | Shin-Chi Chen, Yu-Ze Lin, Huang-Yu Chen | 2025-07-22 |
| 12113051 | Die to die interface circuit | Tze-Chiang Huang, Yu-Hao Liu | 2024-10-08 |
| 12001773 | Automated system and method for circuit design | Shin-Chi Chen, Yu-Ze Lin, Huang-Yu Chen | 2024-06-04 |
| 11699683 | Semiconductor device in 3D stack with communication interface and managing method thereof | Igor Elkanovich, Amnon Parnass, Pei-Ling Yu, Li-Ken Yeh, Yung-Sheng Fang +3 more | 2023-07-11 |
| 11687472 | Interface for semiconductor device and interfacing method thereof | Igor Elkanovich, Amnon Parnass, Pei-Ling Yu, Li-Ken Yeh, Yung-Sheng Fang +3 more | 2023-06-27 |
| 11675731 | Data protection system and method thereof for 3D semiconductor device | Igor Elkanovich, Amnon Parnass, Pei-Ling Yu, Li-Ken Yeh, Yung-Sheng Fang +3 more | 2023-06-13 |
| 11658158 | Die to die interface circuit | Tze-Chiang Huang, Yu-Hao Liu | 2023-05-23 |
| 11620426 | Automated system and method for circuit design | Shin-Chi Chen, Yu-Ze Lin, Huang-Yu Chen | 2023-04-04 |
| 11144485 | Interface for semiconductor device with symmetric bond pattern and method for arranging interface thereof | Igor Elkanovich, Amnon Parnass, Pei-Ling Yu, Li-Ken Yeh, Yung-Sheng Fang +3 more | 2021-10-12 |
| 11031923 | Interface device and interface method for 3D semiconductor device | Igor Elkanovich, Amnon Parnass, Pei-Ling Yu, Li-Ken Yeh, Yung-Sheng Fang +3 more | 2021-06-08 |
| 10467364 | Characterizing cell using input waveforms with different tail characteristics | Yen-Pin Chen, Wen-Hao Chen, Chung-Hsing Wang | 2019-11-05 |
| 10176284 | Semiconductor circuit design and manufacture method | Li-Chung Hsu, Tai-Yu Cheng, Sung-Yen Yeh, Yen-Pin Chen, Chung-Hsing Wang | 2019-01-08 |
| 10169506 | Circuit design method and system | Chung-Hsing Wang, Yen-Pin Chen, Wen-Hao Chen, Chung-Kai Lin, Chih-Hsiang Yao | 2019-01-01 |
| 10055531 | Layout checking method for advanced double patterning photolithography with multiple spacing criteria | Chung-Hsing Wang, Yuan-Te Hou, Chin-Chang Hsu, Meng-Kai Hsu | 2018-08-21 |
| 9563734 | Characterizing cell using input waveform generation considering different circuit topologies | Yen-Pin Chen, Wen-Hao Chen, Chung-Hsing Wang | 2017-02-07 |
| 9509301 | Voltage control of semiconductor integrated circuits | Jerry Chang Jui Kao, Chien-Ju Chao, Chou-Kun Lin, Chin-Shen Lin, Kuo-Nan Yang +1 more | 2016-11-29 |
| 9477803 | Method of generating techfile having reduced corner variation value | Chung-Hsing Wang, Yen-Pin Chen, Wen-Hao Chen, Chung-Kai Lin, Chih-Hsiang Yao | 2016-10-25 |
| 9400866 | Layout modification method and system | Meng-Xiang Lee, Li-Chung Hsu, Shih-Hsien Yang, Ho Che Yu, Chung-Hsing Wang | 2016-07-26 |
| 9311440 | System and method of electromigration avoidance for automatic place-and-route | Jerry Chang Jui Kao, Meng-Xiang Lee, Li-Chung Hsu, Chi-Yeh Yu, Chung-Min Fu +1 more | 2016-04-12 |
| 9201107 | Cell characterization with Miller capacitance | Nitesh Katta, Jerry Chang Jui Kao, Kuo-Nan Yang, Chung-Hsing Wang | 2015-12-01 |
| 9129078 | Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages | Igor Keller, Vinod Kariat | 2015-09-08 |
| 9122839 | Layout modification method and system | Meng-Xiang Lee, Li-Chung Hsu, Shih-Hsien Yang, Ho Che Yu, Chung-Hsing Wang | 2015-09-01 |
| 9058462 | System and method for leakage estimation for standard integrated circuit cells with shared polycrystalline silicon-on-oxide definition-edge (PODE) | Yeh-Chi Chang, Kuo-Nan Yang, Zhe-Wei Jiang, Chung-Hsing Wang | 2015-06-16 |
| 8966421 | Static timing analysis methods for integrated circuit designs using a multi-CCC current source model | Vinod Kariat, Igor Keller, Joel R. Phillips | 2015-02-24 |
| 8826195 | Layout modification method and system | Meng-Xiang Lee, Li-Chung Hsu, Shih-Hsien Yang, Ho Che Yu, Chung-Hsing Wang | 2014-09-02 |