Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12175180 | Systems and methods for context aware circuit design | Li-Chung Hsu, Sung-Yen Yeh, Jerry Chang Jui Kao, Chung-Hsing Wang | 2024-12-24 |
| 12086522 | Method of generating netlist including proximity-effect-inducer (PEI) parameters | Florentin Dartu, Wei-Chih Hsieh, Tzu-Hen Lin, Chung-Hsing Wang | 2024-09-10 |
| 12087690 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-Yuan Chang, Lee-Chung Lu, Li-Chun Tien +6 more | 2024-09-10 |
| 11816413 | Systems and methods for context aware circuit design | Li-Chung Hsu, Sung-Yen Yeh, Jerry Chang Jui Kao, Chung-Hsing Wang | 2023-11-14 |
| 11437319 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-Yuan Chang, Lee-Chung Lu, Li-Chun Tien +6 more | 2022-09-06 |
| 11176305 | Method and system for sigma-based timing optimization | Tzu-Hen Lin, Tai-Yu Cheng, Florentin Dartu, Chung-Hsing Wang | 2021-11-16 |
| 11068637 | Systems and methods for context aware circuit design | Li-Chung Hsu, Sung-Yen Yeh, Jerry Chang Jui Kao, Chung-Hsing Wang | 2021-07-20 |
| 10804200 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-Yuan Chang, Lee-Chung Lu, Li-Chun Tien +6 more | 2020-10-13 |
| 10678989 | Method and system for sigma-based timing optimization | Tzu-Hen Lin, Tai-Yu Cheng, Florentin Dartu, Chung-Hsing Wang | 2020-06-09 |
| 10515166 | Method of timing analysis | Tai-Yu Cheng, Tzu-Hen Lin, Chung-Hsing Wang | 2019-12-24 |
| 10467364 | Characterizing cell using input waveforms with different tail characteristics | King-Ho Tam, Wen-Hao Chen, Chung-Hsing Wang | 2019-11-05 |
| 10176284 | Semiconductor circuit design and manufacture method | Li-Chung Hsu, Tai-Yu Cheng, Sung-Yen Yeh, King-Ho Tam, Chung-Hsing Wang | 2019-01-08 |
| 10169506 | Circuit design method and system | Chung-Hsing Wang, King-Ho Tam, Wen-Hao Chen, Chung-Kai Lin, Chih-Hsiang Yao | 2019-01-01 |
| 10157840 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-Yuan Chang, Lee-Chung Lu, Li-Chun Tien +6 more | 2018-12-18 |
| 9563734 | Characterizing cell using input waveform generation considering different circuit topologies | King-Ho Tam, Wen-Hao Chen, Chung-Hsing Wang | 2017-02-07 |
| 9477803 | Method of generating techfile having reduced corner variation value | Chung-Hsing Wang, King-Ho Tam, Wen-Hao Chen, Chung-Kai Lin, Chih-Hsiang Yao | 2016-10-25 |
| 8914755 | Layout re-decomposition for multiple patterning layouts | Chin-Hsiung Hsu, Huang-Yu Chen, Yuan-Te Hou, Wen-Hao Chen, Chung-Hsing Wang | 2014-12-16 |
| 8826212 | Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed | Sung-Yen Yeh, Yeh-Chi Chang, Zhe-Wei Jiang, King-Ho Tam, Yuan-Te Hou +1 more | 2014-09-02 |
| 8677292 | Cell-context aware integrated circuit design | Chung-Min Fu, Yung-Fong Lu | 2014-03-18 |