Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10872806 | Semiconductor device and manufacturing method thereof | Yi-Chun Huang, Jye-Yen Cheng | 2020-12-22 |
| 10169506 | Circuit design method and system | Chung-Hsing Wang, King-Ho Tam, Yen-Pin Chen, Wen-Hao Chen, Chung-Kai Lin | 2019-01-01 |
| 10170355 | Semiconductor device and manufacturing method thereof | Yi-Chun Huang, Jye-Yen Cheng | 2019-01-01 |
| 9793212 | Interconnect structures and methods of forming same | Yi-Chun Huang, Jye-Yen Cheng, Wen-Chuan Chiang, Ying-Wen Huang | 2017-10-17 |
| 9711391 | Semiconductor device and manufacturing method thereof | Yi-Chun Huang, Jye-Yen Cheng | 2017-07-18 |
| 9477803 | Method of generating techfile having reduced corner variation value | Chung-Hsing Wang, King-Ho Tam, Yen-Pin Chen, Wen-Hao Chen, Chung-Kai Lin | 2016-10-25 |
| 9437485 | Method for line stress reduction through dummy shoulder structures | Cheng-Cheng Kuo, Tzu-Chun Lo, Ming-Hsing Tsai, Ken-Yu Chang, Jye-Yen Cheng +2 more | 2016-09-06 |
| 9209079 | Conductor layout technique to reduce stress-induced void formations | Min-hwa Chi, Tai-Chun Huang | 2015-12-08 |
| 8836141 | Conductor layout technique to reduce stress-induced void formations | Min-hwa Chi, Tai-Chun Huang | 2014-09-16 |
| 8692351 | Dummy shoulder structure for line stress reduction | Cheng-Cheng Kuo, Luke Lo, Minghsing Tsai, Ken-Yu Chang, Jye-Yen Cheng +2 more | 2014-04-08 |
| 8669661 | Metal line and via formation using hard masks | Ying-Wen Huang | 2014-03-11 |
| 8450200 | Method for stacked contact with low aspect ratio | Chen-Hua Yu, Chen-Nan Yeh, Wen-Kai Wan, Jye-Yen Cheng | 2013-05-28 |
| 8435802 | Conductor layout technique to reduce stress-induced void formations | Min-hwa Chi, Tai-Chun Huang | 2013-05-07 |
| 7880303 | Stacked contact with low aspect ratio | Chen-Hua Yu, Chen-Nan Yeh, Wen-Kai Wan, Jye-Yen Cheng | 2011-02-01 |
| 7791070 | Semiconductor device fault detection system and method | Tai-Chun Huang, Kuan-Shou Chi, Wen-Kai Wan | 2010-09-07 |
| 7777338 | Seal ring structure for integrated circuit chips | Tai-Chun Huang, Kuan-Shou Chi, Chih-Cherng Jeng, Ming-Shuoh Liang, Wen-Kai Wan +1 more | 2010-08-17 |
| 7772701 | Integrated circuit having improved interconnect structure | Tai-Chun Huang, Mong-Song Liang | 2010-08-10 |
| 7741714 | Bond pad structure with stress-buffering layer capping interconnection metal layer | Tai-Chun Huang, Wen-Kai Wan | 2010-06-22 |
| 7592710 | Bond pad structure for wire bonding | Chin-Chiu Hsia, Tai-Chun Huang, Chih-Tang Peng | 2009-09-22 |
| 7470994 | Bonding pad structure and method for making the same | Tai-Chun Huang, Chin-Chiu Hsia | 2008-12-30 |
| 7265436 | Non-repeated and non-uniform width seal ring structure | Tai-Chun Huang, Kuan-Shou Chi | 2007-09-04 |
| 7253531 | Semiconductor bonding pad structure | Tai-Chun Huang, Kuan-Shou Chi, Ming-Ta Lei, Chin-Chiu Hsia | 2007-08-07 |
| 7244673 | Integration film scheme for copper / low-k interconnect | Tai-Chun Huang, Yih-Hsiung Lin, Tien-I Bao, Bi-Trong Chen, Yung-Cheng Lu | 2007-07-17 |
| 7151052 | Multiple etch-stop layer deposition scheme and materials | Tai-Chun Huang, Kuan-Shou Chi, Chin-Chiu Hsia, Mong-Song Liang | 2006-12-19 |
| 7098077 | Semiconductor chip singulation method | Tai-Chun Huang, Kuan-Shou Chi | 2006-08-29 |