Issued Patents All Time
Showing 1–25 of 273 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12243773 | Liner and barrier layer in dual damascene cu interconnect for enhanced EM and process | Zhaosheng Meng, Zhuangzhuang Wu | 2025-03-04 |
| 12183795 | Notch shape of trench gate bottom corner for better breakdown voltage of power MOSFET and IGBT with good trade off to ron and ox reliability | Conghui Liu, Peng Li | 2024-12-31 |
| 12154943 | Super junction power device and method of making the same | Conghui Liu, Huan WANG, Longkang Yang | 2024-11-26 |
| 12154944 | Super junction power device | Conghui Liu, Huan WANG, Longkang Yang | 2024-11-26 |
| 12148793 | High voltage semiconductor device comprising a combined junction terminal protection structure with a ferroelectric material | Min Li, Richard Ru-Gin Chang | 2024-11-19 |
| 12136647 | Super junction power device and method of making the same | Conghui Liu, Huan WANG, Longkang Yang, Richard Ru-Gin Chang | 2024-11-05 |
| 12131946 | Method to form contacts with multiple depth by enhanced CESL | Zhaosheng Meng, Xian Zhang | 2024-10-29 |
| 12094873 | SiGe HBT with graphene extrinsic base and methods | Richard Ru-Gin Chang | 2024-09-17 |
| 11984500 | Structure and method of new power MOS and IGBT with built-in multiple VT'S | Dongyang Zhou, Jinpeng Qiu, Peng Li, Conghui Liu | 2024-05-14 |
| 11978702 | Simultaneous self-forming hea barrier and Cu seeding layers for Cu interconnect | Yong Zhao, Zhaosheng Meng | 2024-05-07 |
| 11862674 | High voltage semiconductor device comprising a combined junction terminal protection structure with a ferroelectric material and method of making the same | Min Li, Richard Ru-Gin Chang | 2024-01-02 |
| 11834754 | ALD method with multi-chambers for sic or multi-elements epitaxial growth | Zhaosheng Meng, Zhuangzhuang Wu | 2023-12-05 |
| 11715758 | Super junction power device and method of making the same | Conghui Liu, Huan WANG, Longkang Yang | 2023-08-01 |
| 11677019 | IGBT device with narrow mesa and manufacture thereof | Ching-Ju Lin, Ying-Tsung Wu, Conghui Liu, Longkang Yang, Huan WANG +1 more | 2023-06-13 |
| 11594631 | LDMOS transistor and manufacture thereof | Min Li, Richard Ru-Gin Chang | 2023-02-28 |
| 11462640 | LDMOS transistor having vertical floating field plate and manufacture thereof | Min Li | 2022-10-04 |
| 11456367 | Trench gate structure and method of forming a trench gate structure | Longkang Yang, Huaihua Xu, Huan WANG, Richard Ru-Gin Chang | 2022-09-27 |
| 11011604 | Semiconductor device with recessed source/drain contacts and a gate contact positioned above the active region | Hui Zang | 2021-05-18 |
| 10756213 | FinFET with multilayer fins for multi-value logic (MVL) applications | Ajey Poovannummoottil Jacob, Abhijeet Paul | 2020-08-25 |
| 10622463 | Method, apparatus and system for improved performance using tall fins in finFET devices | Hui Zang, Jinping Liu | 2020-04-14 |
| 10572380 | Structures of bottom select transistor for embedding 3D-NAND in BEOL and methods | Shan Li, Sheng Fen Chiu | 2020-02-25 |
| 10483283 | Flash memory device and manufacture thereof | Shan Li, Sheng Fen Chiu | 2019-11-19 |
| 10475899 | Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby | Ruilong Xie, Andreas Knorr, Julien Frougier, Hui Zang | 2019-11-12 |
| 10438955 | Devices with contact-to-gate shorting through conductive paths between fins and fabrication methods | Hui Zang | 2019-10-08 |
| 10396155 | Semiconductor device with recessed source/drain contacts and a gate contact positioned above the active region | Hui Zang | 2019-08-27 |