Issued Patents All Time
Showing 26–50 of 273 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10388790 | FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming | Ajey Poovannummoottil Jacob, Abhijeet Paul | 2019-08-20 |
| 10347740 | Fin structures and multi-Vt scheme based on tapered fin and method to form | Xusheng Wu, Edmund K. Banghart | 2019-07-09 |
| 10332834 | Semiconductor fuses with nanowire fuse links and fabrication methods thereof | Chun Yu Wong, Jagar Singh, Ashish Baraskar | 2019-06-25 |
| 10297609 | Flash memory device and manufacture thereof | Shan Li, Sheng Fen Chiu | 2019-05-21 |
| 10290654 | Circuit structures with vertically spaced transistors and fabrication methods | Hui Zang, Manfred Eller | 2019-05-14 |
| 10290634 | Multiple threshold voltages using fin pitch and profile | Wen-Pin Peng | 2019-05-14 |
| 10276390 | Method and apparatus for reducing threshold voltage mismatch in an integrated circuit | Meixiong Zhao, Kuniko Kikuta | 2019-04-30 |
| 10269811 | Selective SAC capping on fin field effect transistor structures and related methods | Hui Zang | 2019-04-23 |
| 10243059 | Source/drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins | Srikanth Balaji Samavedan, Manfred Eller, Hui Zang | 2019-03-26 |
| 10204991 | Transistor structures and fabrication methods thereof | Xusheng Wu, Jin Ping Liu | 2019-02-12 |
| 10177157 | Transistor structure having multiple n-type and/or p-type elongated regions intersecting under common gate | Hui Zang | 2019-01-08 |
| 10170377 | Memory cell with recessed source/drain contacts to reduce capacitance | Hui Zang | 2019-01-01 |
| 10170315 | Semiconductor device having local buried oxide | Yanxiang Liu | 2019-01-01 |
| 10170353 | Devices and methods for dynamically tunable biasing to backplates and wells | Hui Zang | 2019-01-01 |
| 10164041 | Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby | Ruilong Xie, Andreas Knorr, Julien Frougier, Hui Zang | 2018-12-25 |
| 10147496 | OTPROM for post-process programming using selective breakdown | Akhilesh Gautam, Suresh Uppal | 2018-12-04 |
| 10147802 | FINFET circuit structures with vertically spaced transistors and fabrication methods | Hui Zang, Manfred Eller | 2018-12-04 |
| 10128333 | FinFET with isolated source and drain | Hoong Shing Wong, Tae Hoon Kim | 2018-11-13 |
| 10121893 | Integrated circuit structure without gate contact and method of forming same | Hui Zang, Manfred Eller, Jerome Ciavatti | 2018-11-06 |
| 10115807 | Method, apparatus and system for improved performance using tall fins in finFET devices | Hui Zang, Jinping Liu | 2018-10-30 |
| 10115738 | Self-aligned back-plane and well contacts for fully depleted silicon on insulator device | Hui Zang | 2018-10-30 |
| 10096604 | Selective SAC capping on fin field effect transistor structures and related methods | Hui Zang | 2018-10-09 |
| 10068766 | Oxidizing and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines | Hui Zang | 2018-09-04 |
| 10056468 | Source/drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins | Srikanth Balaji Samavedan, Manfred Eller, Hui Zang | 2018-08-21 |
| 10056331 | Programmable via devices with metal/semiconductor via links and fabrication methods thereof | Ajey Poovannummoottil Jacob, Suraj K. Patil | 2018-08-21 |