Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11171036 | Preventing dielectric void over trench isolation region | Yongjun Shi, Wei Hong, Halting Wang, Liu Jiang | 2021-11-09 |
| 11018221 | Air gap regions of a semiconductor device | Haiting Wang, Yong Shi, Xiaoming Yang, Liu Jiang | 2021-05-25 |
| 10910276 | STI structure with liner along lower portion of longitudinal sides of active region, and related FET and method | Yongjun Shi, Xinyuan Dou, Hongliang Shen, Baofu Zhu | 2021-02-02 |
| 10879171 | Vertically oriented metal silicide containing e-fuse device | Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang | 2020-12-29 |
| 10804199 | Self-aligned chamferless interconnect structures of semiconductor devices | Yongjun Shi, Ruilong Xie, Nan Fu | 2020-10-13 |
| 10636894 | Fin-type transistors with spacers on the gates | Yanping Shen, Hui Zang, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti +4 more | 2020-04-28 |
| 10510662 | Vertically oriented metal silicide containing e-fuse device and methods of making same | Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang | 2019-12-17 |
| 10475791 | Transistor fins with different thickness gate dielectric | Hui Zang, Garo Derderian, Laertis Economikos, Jiehui Shu, Shesh Mani Pandey | 2019-11-12 |
| 10468481 | Self-aligned single diffusion break isolation with reduction of strain loss | Haiting Wang, Hui Zang, Kwan-Yong Lim | 2019-11-05 |
| 10461029 | Hybrid material electrically programmable fuse and methods of forming | Jagar Singh | 2019-10-29 |
| 10439026 | Fins with single diffusion break facet improvement using epitaxial insulator | Hui Zang, Xusheng Wu | 2019-10-08 |
| 10418285 | Fin field-effect transistor (FinFET) and method of production thereof | Hui Zang, Laertis Economikos | 2019-09-17 |
| 10332834 | Semiconductor fuses with nanowire fuse links and fabrication methods thereof | Jagar Singh, Ashish Baraskar, Min-hwa Chi | 2019-06-25 |
| 10043764 | Through silicon via device having low stress, thin film gaps and methods for forming the same | Huang Liu, Sarasvathi Thangaraju | 2018-08-07 |
| 9761481 | Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via | Sarasvathi Thangaraju, Percival Rayo | 2017-09-12 |
| 9706832 | Dispensers and applicator heads therefor | Amy Marie Price, Gregory Clegg Spooner, Kin Wong Yau, Ming Fung Chen, William F. Jones +2 more | 2017-07-18 |
| 9601428 | Semiconductor fuses with nanowire fuse links and fabrication methods thereof | Jagar Singh, Ashish Baraskar, Min-hwa Chi | 2017-03-21 |
| 9508795 | Methods of fabricating nanowire structures | Min-hwa Chi, Ashish Baraskar, Jagar Singh | 2016-11-29 |
| 9455188 | Through silicon via device having low stress, thin film gaps and methods for forming the same | Huang Liu, Sarasvathi Thangaraju | 2016-09-27 |
| 9245790 | Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via | Sarasvathi Thangaraju | 2016-01-26 |
| 8637993 | 3D integrated circuit system with connecting via structure and method for forming the same | Ramakanth Alapati, Teck Jung Tang | 2014-01-28 |