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Gate capping layers of semiconductor devices |
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STI structure with liner along lower portion of longitudinal sides of active region, and related FET and method |
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Integrated circuit structure to reduce soft-fail incidence and method of forming same |
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Method of forming smooth sidewall structures using spacer materials |
Ravi Prakash Srivastava, Sipeng Gu, Sunil Kumar Singh, Akshey Sehgal, Zhiguo Sun |
2020-07-14 |
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Method to reduce FinFET short channel gate height |
Hong Yu, Zhenyu Hu, Xing Zhang |
2020-05-05 |
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Method to form high performance fin profile for 12LP and above |
Yanzhen Wang, Hongliang Shen, Sipeng Gu |
2020-03-03 |
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Selective shallow trench isolation (STI) fill for stress engineering in semiconductor structures |
Ashish Jha, Hong Yu, Xusheng Wu, Dongil Choi, Edmund K. Banghart +1 more |
2019-12-31 |
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Middle of the line (MOL) contact formation method and structure |
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2019-07-09 |
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Methods, apparatus, and system for fabricating finFET devices with increased breakdown voltage |
Yanzhen Wang, Sipeng Gu |
2018-12-11 |
| 10090382 |
Integrated circuit structure including single diffusion break and end isolation region, and methods of forming same |
Hong Yu, Hui Zhan, Zhenyu Hu |
2018-10-02 |
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Semiconductor structure with uniform gate heights |
Xing Zhang, Hong Yu, Zhenyu Hu |
2018-09-25 |
| 10074732 |
Methods of forming short channel and long channel finFET devices so as to adjust threshold voltages |
Hui Zang, Hong Yu, Yanzhen Wang |
2018-09-11 |
| 10043713 |
Method to reduce FinFET short channel gate height |
Hong Yu, Zhenyu Hu, Xing Zhang |
2018-08-07 |
| 10014296 |
Fin-type field effect transistors with single-diffusion breaks and method |
Hong Yu, Sipeng Gu, Yanzhen Wang |
2018-07-03 |
| 9831098 |
Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealing |
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2017-11-28 |
