Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10347531 | Middle of the line (MOL) contact formation method and structure | Sipeng Gu, Xusheng Wu, Xinyuan Dou, Xiaobo Chen, Guoliang Zhu +1 more | 2019-07-09 |
| 10026818 | Field effect transistor structure with recessed interlayer dielectric and method | Sipeng Gu, Xusheng Wu, Jeffrey Chee | 2018-07-17 |
| 8624329 | Spacer-less low-K dielectric processes | Yong Meng Lee, Young Way Teh, Chung Woh Lai, Khee Yong Lim, Wee Leng Tan +3 more | 2014-01-07 |
| 8519445 | Poly profile engineering to modulate spacer induced stress for device enhancement | Vincent Ho, Young Way Teh, Yong Kong Siew, Bei Chao Zhang, Fan Zhang +2 more | 2013-08-27 |
| 8148221 | Double anneal with improved reliability for dual contact etch stop liner scheme | Khee Yong Lim, Victor Chan, Eng Hua Lim, Jamin F. Fen | 2012-04-03 |
| 7999325 | Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS | Young Way Teh, Yong Meng Lee, Chung Woh Lai, Khee Yong Lim, Wee Leng Tan +3 more | 2011-08-16 |
| 7993997 | Poly profile engineering to modulate spacer induced stress for device enhancement | Vincent Ho, Young Way Teh, Yong Kong Siew, Bei Chao Zhang, Fan Zhang +2 more | 2011-08-09 |
| 7977185 | Method and apparatus for post silicide spacer removal | Brian J. Greene, Chung Woh Lai, Yong Meng Lee, Siddhartha Panda, Kern Rim +1 more | 2011-07-12 |
| 7615427 | Spacer-less low-k dielectric processes | Yong Meng Lee, Young Way Teh, Chung Woh Lai, Khee Yong Lim, Wee Leng Tan +3 more | 2009-11-10 |
| 7615433 | Double anneal with improved reliability for dual contact etch stop liner scheme | Khee Yong Lim, Victor Chan, Eng Hua Lim, Jamin F. Fen | 2009-11-10 |
| 7445978 | Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS | Young Way Teh, Yong Meng Lee, Chung Woh Lai, Khee Yong Lim, Wee Leng Tan +3 more | 2008-11-04 |
| 7256084 | Composite stress spacer | Khee Yong Lim, Chung Woh Lai, Yong Meng Lee, Liang-Choo Hsia, Young Way Teh +3 more | 2007-08-14 |
| 7022625 | Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration | Chew Hoe Ang, Alan Lek | 2006-04-04 |
| 7005716 | Dual metal gate process: metals and their silicides | Mei Sheng Zhou, Kin Leong Pey, Simon Chooi | 2006-02-28 |
| 6891233 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Mei Sheng Zhou, Kin Leong Pey, Simon Chooi | 2005-05-10 |
| 6835989 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Mei Sheng Zhou, Kin Leong Pey, Simon Chooi | 2004-12-28 |
| 6750519 | Dual metal gate process: metals and their silicides | Mei Sheng Zhou, Kin Leong Pey, Simon Chooi | 2004-06-15 |
| 6743291 | Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth | Chew Hoe Ang, Jia Zhen Zheng | 2004-06-01 |
| 6709912 | Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization | Chew Hoe Ang, Jeffrey Chee Wei-Lun, Jia Zhen Zheng | 2004-03-23 |
| 6677652 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Mei Sheng Zhou, Kin Leong Pey, Simon Chooi | 2004-01-13 |
| 6670248 | Triple gate oxide process with high-k gate dielectric | Chew Hoe Ang, Jia Zhen Zheng | 2003-12-30 |
| 6664156 | Method for forming L-shaped spacers with precise width control | Chew Hoe Ang, Eng Hua Lim, Jia Zhen Zheng | 2003-12-16 |
| 6534388 | Method to reduce variation in LDD series resistance | Zhong Dong, Simon Chooi, Kin Leong Pey | 2003-03-18 |
| 6524910 | Method of forming dual thickness gate dielectric structures via use of silicon nitride layers | Kin Leong Pey, Mei Sheng Zhou, Zhong Dong, Simon Chooi | 2003-02-25 |
| 6486080 | Method to form zirconium oxide and hafnium oxide for high dielectric constant materials | Simon Chooi, Mei Sheng Zhou | 2002-11-26 |