Issued Patents All Time
Showing 1–25 of 144 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8860142 | Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction | Debora Chyiu Hyia Poon, Alex See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan +1 more | 2014-10-14 |
| 8754447 | Strained channel transistor structure and method | Jin Ping Liu, Alex See, Liang-Choo Hsia | 2014-06-17 |
| 8716076 | Method for fabricating a semiconductor device having an epitaxial channel and transistor having same | Jinping Liu, Alex See, Liang-Choo Hsia | 2014-05-06 |
| 8546873 | Integrated circuit and method of fabrication thereof | Jinping Liu, Hai Cong, Binbin Zhou, Alex See, Liang-Choo Hsia | 2013-10-01 |
| 8415236 | Methods for reducing loading effects during film formation | Han-Guan Chew, Jinping Liu, Alex See | 2013-04-09 |
| 8394724 | Processing with reduced line end shortening ratio | Hai Cong, Wei Loong Loh, Krishan Gopal, Xin Ji Zhang, Pradeep Ramachandramurthy Yelehanka | 2013-03-12 |
| 8354347 | Method of forming high-k dielectric stop layer for contact hole opening | Jianhui Ye, Huang Liu, Alex See, Wei Lu, Chun Hui Low +2 more | 2013-01-15 |
| 8324011 | Implementation of temperature-dependent phase switch layer for improved temperature uniformity during annealing | Chyiu Hyia Poon, Alex See | 2012-12-04 |
| 8293544 | Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction | Debora Chyiu Hyia Poon, Alex See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan +1 more | 2012-10-23 |
| 8058123 | Integrated circuit and method of fabrication thereof | Jinping Liu, Hai Cong, Binbin Zhou, Alex See, Liang-Choo Hsia | 2011-11-15 |
| 8012839 | Method for fabricating a semiconductor device having an epitaxial channel and transistor having same | Jinping Liu, Alex See, Liang-Choo Hsia | 2011-09-06 |
| 7966142 | Multi-variable regression for metrology | Wen-Zhan Zhou, Zheng Zou, Jasper Goh | 2011-06-21 |
| 7960283 | Method for reducing silicide defects in integrated circuits | Jeff Jianhui Ye, Huang Liu, Alex See, Wei Lu, Hai Cong +2 more | 2011-06-14 |
| 7902066 | Damascene contact structure for integrated circuits | Jian Ye | 2011-03-08 |
| 7879732 | Thin film etching method and semiconductor device fabrication using same | Xiang Hu, Hai Cong, Pradeep Ramachandramurthy Yelehanka | 2011-02-01 |
| 7776699 | Strained channel transistor structure and method | Jin Ping Liu, Alex See, Liang-Choo Hsia | 2010-08-17 |
| 7745320 | Method for reducing silicide defects in integrated circuits | Jeff Jianhui Ye, Huang Liu, Alex See, Wei Lu, Hai Cong +2 more | 2010-06-29 |
| 7452808 | Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding | Simon Chooi, Yakub Aliyu, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy +2 more | 2008-11-18 |
| 7354623 | Surface modification of a porous organic material through the use of a supercritical fluid | Ching-Ya Wang, Ping Chuang, Sunny Wu, Yu-Liang Lin, Hung-Jung Tu +1 more | 2008-04-08 |
| 7338909 | Micro-etching method to replicate alignment marks for semiconductor wafer photolithography | Yu-Liang Lin, Henry Lo, Chung-Long Chang, Gorge Huang, Tony Lu +8 more | 2008-03-04 |
| 7179879 | Poly(arylene ether) dielectrics | Christopher Lim, Siu Choon Ng, Hardy Chan, Simon Chooi | 2007-02-20 |
| 7166250 | Poly(arylene ether) dielectrics | Christopher Lim, Siu Choon Ng, Hardy Chan, Simon Chooi | 2007-01-23 |
| 7083495 | Advanced process control approach for Cu interconnect wiring sheet resistance control | Chun-Hsien Lin, Ai-Sen Liu, Sunny Wu, Yu-Liang Lin, Henry Lo | 2006-08-01 |
| 7071281 | Poly(arylene ether) dielectrics | Christopher Lim, Siu Choon Ng, Hardy Chan, Simon Chooi | 2006-07-04 |
| 7060613 | Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding | Simon Chooi, Yakub Aliyu, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy +2 more | 2006-06-13 |