Issued Patents All Time
Showing 1–25 of 82 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10910471 | Device with large EPI in FinFETs and method of manufacturing | Jianwei Peng, Sang Woo Lim, Matthew W. Stoker, Jinping Liu | 2021-02-02 |
| 10854472 | Method for forming a metal gate including de-oxidation of an oxidized surface of the metal gate utilizing a reducing agent | Wen-Pin Peng, Jean-Baptiste Laloe | 2020-12-01 |
| 10559470 | Capping structure | Haigou Huang, Jinsheng Gao, Hong Yu, Jinping Liu | 2020-02-11 |
| 10173167 | Composite method of trapping carbon dioxide in gas mixture | Guangjin Chen, Bei Liu, Changyu Sun, Xueteng Gao | 2019-01-08 |
| 10103097 | CD control | Zheng Zou, Alex See, Hai Cong | 2018-10-16 |
| 10056458 | Siloxane and organic-based MOL contact patterning | Chang Ho Maeng, Andy Wei, Anthony Ozzello, Bharat Krishnan, Guillaume Bouche +9 more | 2018-08-21 |
| 10043764 | Through silicon via device having low stress, thin film gaps and methods for forming the same | Sarasvathi Thangaraju, Chun Yu Wong | 2018-08-07 |
| 9793169 | Methods for forming mask layers using a flowable carbon-containing silicon dioxide material | Huy Cao, Guillaume Bouche, Songkram Srivathanakul | 2017-10-17 |
| 9754837 | Controlling within-die uniformity using doped polishing material | Haigou Huang, Jinping Liu, Taifong Chao | 2017-09-05 |
| 9666476 | Dimension-controlled via formation processing | Xiang Hu, Yuping Ren, Duohui Bei, Sipeng Gu | 2017-05-30 |
| 9627274 | Methods of forming self-aligned contacts on FinFET devices | Haifeng Sheng, Xintuo Dai, Jinping Liu | 2017-04-18 |
| 9620381 | Facilitating etch processing of a thin film via partial implantation thereof | Suraj K. Patil, Huy Cao, Hui Zhan | 2017-04-11 |
| 9620380 | Methods for fabricating integrated circuits using self-aligned quadruple patterning | Xintuo Dai, Jin Ping Liu, Jiong Li | 2017-04-11 |
| 9606432 | Alternating space decomposition in circuit structure fabrication | Guoxiang Ning, Xintuo Dai, Chin Teong Lim | 2017-03-28 |
| 9595493 | Reducing liner corrosion during metallization of semiconductor devices | Zhiguo Sun, Qiang Fang, Haigou Huang, Jiehui Shu, Jin Ping Liu | 2017-03-14 |
| 9589807 | Method for eliminating interlayer dielectric dishing and controlling gate height uniformity | Haigou Huang, Jinping Liu, Yuanfang Lu | 2017-03-07 |
| 9502232 | Inhibiting diffusion of elements between material layers of a layered circuit structure | Sipeng Gu, Sandeep Gaan, Zhiguo Sun, Adam Selsley | 2016-11-22 |
| 9490129 | Integrated circuits having improved gate structures and methods for fabricating same | Xiang Hu | 2016-11-08 |
| 9478625 | Metal resistor using FinFET-based replacement gate process | Hui Zang, Min-hwa Chi | 2016-10-25 |
| 9466723 | Liner and cap layer for placeholder source/drain contact structure planarization and replacement | Haigou Huang, Qiang Fang, Jin Ping Liu | 2016-10-11 |
| 9455188 | Through silicon via device having low stress, thin film gaps and methods for forming the same | Sarasvathi Thangaraju, Chun Yu Wong | 2016-09-27 |
| 9455204 | 10 nm alternative N/P doped fin for SSRW scheme | Huy Cao, Jinping Liu, Guillaume Bouche | 2016-09-27 |
| 9443956 | Method for forming air gap structure using carbon-containing spacer | Hong Yu, Biao Zuo, Jin Ping Liu | 2016-09-13 |
| 9431528 | Lithographic stack excluding SiARC and method of using same | Hong Yu, Xiang Hu, Zhao Lun | 2016-08-30 |
| 9425127 | Method for forming an air gap around a through-silicon via | Hong Yu | 2016-08-23 |