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Lithographic stack excluding SiARC and method of using same |
Hong Yu, Xiang Hu, Huang Liu |
2016-08-30 |
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Multi-layer spacer used in finFET |
Jianwei Peng, Hong Yu, Tao Han, Hsien-Ching Lo, Basab Banerjee +2 more |
2016-08-16 |
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Uniform exposed raised structures for non-planar semiconductor devices |
Hong Yu, Hongliang Shen, Zhenyu Hu, Richard J. Carter |
2016-06-07 |
| 9337306 |
Multi-phase source/drain/gate spacer-epi formation |
Jianwei Peng, Xusheng Wu, Hong Yu |
2016-05-10 |
| 9059218 |
Reducing gate expansion after source and drain implant in gate last process |
Bharat Krishnan, Jinping Liu, Hui Zhan, Bongki Lee |
2015-06-16 |
| 8987083 |
Uniform gate height for semiconductor structure with N and P type fins |
Zhenyu Hu, Xing Zhang |
2015-03-24 |
| 8716081 |
Capacitor top plate over source/drain to form a 1T memory device |
Lee-Wee Teo, Yong Meng Lee, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee +2 more |
2014-05-06 |
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Hybrid orientation substrate with stress layer |
Lee-Wee Teo, Chung Woh Lai, Johnny Widodo, Shyue Seng Tan, Shailendra Mishra +2 more |
2012-09-25 |
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Method of forming shallow trench isolation structures for integrated circuits |
Shailendra Mishra, James Yong Meng Lee, Wen Zhi Gao, Chung Woh Lai, Huang Liu +2 more |
2012-05-15 |
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Nested and isolated transistors with reduced impedance difference |
Johnny Widodo, Liang-Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Huang Liu +5 more |
2012-03-27 |
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Method of manufacture of an integrated circuit system with self-aligned isolation structures |
Shailendra Mishra, Lee-Wee Teo, Yong Meng Lee, Chung Woh Lai, Shyue Seng Tan +2 more |
2011-11-08 |
| 7999300 |
Memory cell structure and method for fabrication thereof |
James Yong Meng Lee, Lee-Wee Teo, Shyue Seng Tan, Chung Woh Lai, Johnny Widodo +2 more |
2011-08-16 |
| 7932178 |
Integrated circuit having a plurality of MOSFET devices |
Lee-Wee Teo, Yong Meng Lee, Jeffrey Chee, Shyue Seng Tan, Chung Woh Lai +2 more |
2011-04-26 |
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Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein |
Jun Jung Kim, Joo-chan Kim, Jae-eon Park, Richard A. Conti, Johnny Widodo +2 more |
2010-11-23 |
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Integrated circuit system employing selective epitaxial growth technology |
Huang Liu, Alex See, James Yong Meng Lee, Johnny Widodo, Chung Woh Lai +3 more |
2010-09-14 |
| 7767577 |
Nested and isolated transistors with reduced impedance difference |
Johnny Widodo, Liang-Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Huang Liu +5 more |
2010-08-03 |
| 7485524 |
MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the same |
Zhijiong Luo, Yung Fu Chong, Judson R. Holt, Huilong Zhu |
2009-02-03 |
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Semiconductor device and fabrication method |
Purakh Raj Verma, Liang-Choo Hsia, Dong Kyun Sohn, Guowei Zhang, Chew Hoe Ang +3 more |
2008-02-05 |
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Shallow low energy ion implantation into pad oxide for improving threshold voltage stability |
Yisuo Li, Francis Benistant, Kim Sik |
2007-08-21 |
| 6998682 |
Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension |
Yeen Tat Chan, Kheng Chok Tee, Yiang Aun Nga, Wang Ling Goh, Diing Shenp Ang |
2006-02-14 |
| 6905919 |
Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension |
Yeen Tat Chan, Kheng Chok Tee, Yiang Aun Nga, Wang Ling Goh, Diing Shenp Ang |
2005-06-14 |
