Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9502413 | Semiconductor devices including raised source/drain stressors and methods of manufacturing the same | Se-Chan Lim, Sang-Pil Sim, Su-Youn Yi | 2016-11-22 |
| 9425148 | Semiconductor devices having contacts with intervening spacers and method for fabricating the same | Ho Jun Kim, Hae-Wang Lee, Chul-Hong Park, Jong Shik Yoon | 2016-08-23 |
| 9147654 | Integrated circuit system employing alternating conductive layers | Haifeng Sheng, Fan Zhang, Juan Boon Tan, Bei Chao Zhang | 2015-09-29 |
| 8358007 | Integrated circuit system employing low-k dielectrics and method of manufacture thereof | Wuping Liu, Fan Zhang, Juan Boon Tan, Jing Hui Li, Bei Chao Zhang +3 more | 2013-01-22 |
| 8283263 | Integrated circuit system including nitride layer technology | Sripad Sheshagiri Nagarad, Hwa Weng Koh, Xiaoyu Chen, Louis Lim, Sung Mun Jung +3 more | 2012-10-09 |
| 8034670 | Reliable memory cell | Timothy Phua, Bangun Indajang | 2011-10-11 |
| 8008744 | Selective STI stress relaxation through ion implantation | Lee-Wee Teo, Shiang Yang Ong, Jae Gon Lee, Vincent Leong, Elgin Quek | 2011-08-30 |
| 7888214 | Selective stress relaxation of contact etch stop layer through layout design | Lee-Wee Teo, Elgin Quek | 2011-02-15 |
| 7727856 | Selective STI stress relaxation through ion implantation | Lee-Wee Teo, Shiang Yang Ong, Jae Gon Lee, Vincent Leong, Elgin Quek | 2010-06-01 |
| 7645687 | Method to fabricate variable work function gates for FUSI devices | Yung Fu Chong, Chew-Hue Ang, Purakh Raj Vermo, Liang-Choo Hsia | 2010-01-12 |
| 7585746 | Process integration scheme of SONOS technology | Sung Mun Jung, Yoke Leng Lim, Sripad Sheshagiri Nagarad, Dong Hua Liu, Xiao Chen +1 more | 2009-09-08 |
| 7479425 | Method for forming high-K charge storage device | Chew Hoe Ang, Liang-Choo Hsia | 2009-01-20 |
| 7338886 | Implantation-less approach to fabricating strained semiconductor on isolation wafers | Jinping Liu, Liang-Choo Hsia | 2008-03-04 |
| 7326609 | Semiconductor device and fabrication method | Purakh Raj Verma, Liang-Choo Hsia, Guowei Zhang, Chew Hoe Ang, Yun Ling Tan +3 more | 2008-02-05 |
| 7256112 | Laser activation of implanted contact plug for memory bitline fabrication | Yung Fu Chong, Liang-Choo Hsia | 2007-08-14 |
| 7202140 | Method to fabricate Ge and Si devices together for performance enhancement | Chew Hoe Ang, Liang-Choo Hsia | 2007-04-10 |
| 7202164 | Method of forming ultra thin silicon oxynitride for gate dielectric applications | Jinping Liu, Hwa Weng Koh, Liang-Choo Hsia | 2007-04-10 |
| 7166522 | Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch | Jin Ping Liu, Liang-Choo Hsia | 2007-01-23 |
| 7029976 | Method for SONOS EFLASH integrated circuit | Sripad Sheshagiri Nagarad, Yoke Leng Lim, Siow Lee Chwa, Hsiang Fang Lim | 2006-04-18 |
| 6995078 | Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch | Jin Ping Liu, Liang-Choo Hsia | 2006-02-07 |
| 6946349 | Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses | Jae Gon Lee, Hwa Weng Koh, Elgin Quek | 2005-09-20 |
| 6885103 | Semiconductor device including ternary phase diffusion barrier | Ji-Soo Park, Jong-Uk Bae | 2005-04-26 |
| 6649520 | Method of forming film for reduced ohmic contact resistance and ternary phase layer amorphous diffusion barrier | Ji-Soo Park, Jong-Uk Bae | 2003-11-18 |
| 6528401 | Method for fabricating polycide dual gate in semiconductor device | Jong-Uk Bae, Ji-Soo Park | 2003-03-04 |
| 6489210 | Method for forming dual gate in DRAM embedded with a logic circuit | Jeong-Mo Hwang | 2002-12-03 |