Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9490165 | Reliable interconnect integration scheme | Luying Du, Fan Zhang, Jun Chen, Juan Boon Tan | 2016-11-08 |
| 9147654 | Integrated circuit system employing alternating conductive layers | Haifeng Sheng, Fan Zhang, Juan Boon Tan, Dong Kyun Sohn | 2015-09-29 |
| 8519445 | Poly profile engineering to modulate spacer induced stress for device enhancement | Vincent Ho, Wenhe Lin, Young Way Teh, Yong Kong Siew, Fan Zhang +2 more | 2013-08-27 |
| 8358007 | Integrated circuit system employing low-k dielectrics and method of manufacture thereof | Dong Kyun Sohn, Wuping Liu, Fan Zhang, Juan Boon Tan, Jing Hui Li +3 more | 2013-01-22 |
| 8177993 | Apparatus and methods for cleaning and drying of wafers | Boon Meng Seah, Raymond Joy, Shao Beng Law, John Sudijono, Liang-Choo Hsia | 2012-05-15 |
| 8115276 | Integrated circuit system employing back end of line via techniques | Shaoqing Zhang, Fan Zhang, Shao-fu Sanford Chu | 2012-02-14 |
| 8102054 | Reliable interconnects | Chim Seng Seet, Juan Boon Tan, Fan Zhang, Yong Chiang EE, Bo Tao +2 more | 2012-01-24 |
| 7993997 | Poly profile engineering to modulate spacer induced stress for device enhancement | Vincent Ho, Wenhe Lin, Young Way Teh, Yong Kong Siew, Fan Zhang +2 more | 2011-08-09 |
| 7947604 | Method for corrosion prevention during planarization | Fan Zhang, Lup San Leong, Yong Kong Siew | 2011-05-24 |
| 7803704 | Reliable interconnects | Chim Seng Seet, Juan Boon Tan, Fan Zhang, Yong Chiang EE, Bo Tao +2 more | 2010-09-28 |
| 7781895 | Via electromigration improvement by changing the via bottom geometric profile | Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo | 2010-08-24 |
| 7691739 | Via electromigration improvement by changing the via bottom geometric profile | Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo | 2010-04-06 |
| 7678586 | Structure and method to prevent charge damage from e-beam curing process | Huang Liu, Wuping Liu, John Sudijono, Liang-Choo Hsia | 2010-03-16 |
| 7622403 | Semiconductor processing system with ultra low-K dielectric | Yasri Yudhistira, Johnny Widodo, Liang-Choo Hsia | 2009-11-24 |
| 7524755 | Entire encapsulation of Cu interconnects using self-aligned CuSiN film | Johnny Widodo, Tong Qing Chen, Yong Kong Siew, Fan Zhang, San Leong Liew +2 more | 2009-04-28 |
| 7372156 | Method to fabricate aligned dual damascene openings | Yeow Kheng Lim, Wuping Liu, Tae Jong Lee, Juan Boon Tan, Alan Cuthbertson +1 more | 2008-05-13 |
| 7294241 | Method to form alpha phase Ta and its application to IC manufacturing | Chim Seng Seet, San Leong Liew, John Sudijono, Lai Lin Clare Yong | 2007-11-13 |
| 7276440 | Method of fabrication of a die oxide ring | Fan Zhang, Wuping Liu, Kho Liep Chok, Liang-Choo Hsia, Tae Jong Lee +2 more | 2007-10-02 |
| 7256136 | Self-patterning of photo-active dielectric materials for interconnect isolation | Wuping Liu, Liang-Choo Hsia | 2007-08-14 |
| 7012022 | Self-patterning of photo-active dielectric materials for interconnect isolation | Wuping Liu, Liang-Choo Hsia | 2006-03-14 |
| 6995087 | Integrated circuit with simultaneous fabrication of dual damascene via and trench | Wuping Liu, Juan Boon Tan, Alan Cuthbertson | 2006-02-07 |
| 6967156 | Method to fabricate aligned dual damascene openings | Yeow Kheng Lim, Wuping Liu, Tae Jong Lee, Juan Boon Tan, Alan Cuthbertson +1 more | 2005-11-22 |
| 6517235 | Using refractory metal silicidation phase transition temperature points to control and/or calibrate RTP low temperature operation | Zhong Yun Zhu, Rajneesh Jaiswal, Haznita Abd Karim, Johnny Cham, Ravi Sankar Yelamanchi +1 more | 2003-02-11 |
| 6383922 | Thermal stability improvement of CoSi2 film by stuffing in titanium | Chung Woh Lai, Eng Hua Lim, Mei Sheng Zhou, Peter Chew, Arthur Ang | 2002-05-07 |