Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8148221 | Double anneal with improved reliability for dual contact etch stop liner scheme | Khee Yong Lim, Victor Chan, Wenhe Lin, Jamin F. Fen | 2012-04-03 |
| 7615433 | Double anneal with improved reliability for dual contact etch stop liner scheme | Khee Yong Lim, Victor Chan, Wenhe Lin, Jamin F. Fen | 2009-11-10 |
| 7545004 | Method and structure for forming strained devices | Haining Yang | 2009-06-09 |
| 7396724 | Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals | Victor Chan, Haining Yang, Yong Meng Lee | 2008-07-08 |
| 6841441 | Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing | Chew Hoe Ang, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more | 2005-01-11 |
| 6828082 | Method to pattern small features by using a re-flowable hard mask | Chew Hoe Ang, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more | 2004-12-07 |
| 6762085 | Method of forming a high performance and low cost CMOS device | Jia Zhen Zheng, Soh Yun Siah, Liang-Choo Hsia, Simon Chooi, Chew Hoe Ang | 2004-07-13 |
| 6664156 | Method for forming L-shaped spacers with precise width control | Chew Hoe Ang, Wenhe Lin, Jia Zhen Zheng | 2003-12-16 |
| 6664153 | Method to fabricate a single gate with dual work-functions | Chew Hoe Ang, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more | 2003-12-16 |
| 6653227 | Method of cobalt silicidation using an oxide-Titanium interlayer | Chung Woh Lai, Beichao Zhang, Arthur Ang, Hai Jiang Peng, Charles Lin | 2003-11-25 |
| 6632712 | Method of fabricating variable length vertical transistors | Chew Hoe Ang, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more | 2003-10-14 |
| 6632745 | Method of forming almost L-shaped spacer for improved ILD gap fill | Chiew Wah Yap, Zheng Zou, Nguyen Lac, Yelehanka Ramachandramurthy Pradeep, Manni Lal | 2003-10-14 |
| 6610604 | Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask | Chew Hoe Ang, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more | 2003-08-26 |
| 6610575 | Forming dual gate oxide thickness on vertical transistors by ion implantation | Chew Hoe Ang, Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more | 2003-08-26 |
| 6605501 | Method of fabricating CMOS device with dual gate electrode | Chew Hoe Ang, Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou | 2003-08-12 |
| 6544848 | Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers | Chew Hoe Ang, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more | 2003-04-08 |
| 6468851 | Method of fabricating CMOS device with dual gate electrode | Chew Hoe Ang, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more | 2002-10-22 |
| 6429109 | Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate | Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou, Daniel Yen, Chew Hoe Ang +1 more | 2002-08-06 |
| 6383922 | Thermal stability improvement of CoSi2 film by stuffing in titanium | Bei Chao Zhang, Chung Woh Lai, Mei Sheng Zhou, Peter Chew, Arthur Ang | 2002-05-07 |
| 6350661 | Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts | Chong Wee Lim, Soh Yun Siah, Kong Hean Lee, Chun Hui Low | 2002-02-26 |
| 6297126 | Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts | Chong Wee Lim, Soh Yun Siah, Kong Hean Lee, Chun Hui Low | 2001-10-02 |
| 6271133 | Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication | Chong Wee Lim, Kin Leong Pey, Soh Yun Siah, Chun Hui Low | 2001-08-07 |
| 6265302 | Partially recessed shallow trench isolation method for fabricating borderless contacts | Chong Wee Lim, Soh Yun Siah, Kong Hean Lee, Chun Hui Low | 2001-07-24 |
| 6228727 | Method to form shallow trench isolations with rounded corners and reduced trench oxide recess | Chong Wee Lim, Soh Yun Siah, Kong Hean Lee, Chun Hui Low | 2001-05-08 |
| 6165871 | Method of making low-leakage architecture for sub-0.18 .mu.m salicided CMOS device | Chong Wee Lim, Soh Yun Siah, Kong Hean Lee, Pei Ching Lee | 2000-12-26 |