Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6649486 | Method to form shallow trench isolations | Subramanian Balakumar, Zheng Zhou, Xian Bin Wang | 2003-11-18 |
| 6613648 | Shallow trench isolation using TEOS cap and polysilicon pullback | Seng-Keong Victor Lim, Feng Chen, Wang Ling Goh | 2003-09-02 |
| 6410429 | Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions | Chaw Sing Ho, Kheng Chok Tee, Kin Leong Pey, G. Karunasiri, Soo Jin Chua +1 more | 2002-06-25 |
| 6350661 | Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts | Chong Wee Lim, Eng Hua Lim, Soh Yun Siah, Chun Hui Low | 2002-02-26 |
| 6297126 | Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts | Chong Wee Lim, Eng Hua Lim, Soh Yun Siah, Chun Hui Low | 2001-10-02 |
| 6265302 | Partially recessed shallow trench isolation method for fabricating borderless contacts | Chong Wee Lim, Eng Hua Lim, Soh Yun Siah, Chun Hui Low | 2001-07-24 |
| 6258676 | Method for forming a shallow trench isolation using HDP silicon oxynitride | Peter Chew | 2001-07-10 |
| 6228727 | Method to form shallow trench isolations with rounded corners and reduced trench oxide recess | Chong Wee Lim, Soh Yun Siah, Eng Hua Lim, Chun Hui Low | 2001-05-08 |
| 6165871 | Method of making low-leakage architecture for sub-0.18 .mu.m salicided CMOS device | Eng Hua Lim, Chong Wee Lim, Soh Yun Siah, Pei Ching Lee | 2000-12-26 |
| 6010954 | Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices | Chaw Sing Ho, R. P.G. Karunasiri, Soo Jin Chua, Kin Leong Pey | 2000-01-04 |
| 5956137 | In-line process monitoring using micro-raman spectroscopy | Eng Hua Lim, Kin Leong Pey, Harianto Wong | 1999-09-21 |