Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11158646 | Memory device with dielectric blocking layer for improving interpoly dielectric breakdown | — | 2021-10-26 |
| 11119917 | Neuromorphic memories with split gate flash multi-level cell and method of making the same | Danny Pak-Chum Shum, Shyue Seng Tan, Xinshu Cai, Fan Zhang, Tze Ho Simon Chan | 2021-09-14 |
| 10608046 | Integrated two-terminal device with logic device for embedded application | Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Hai Cong, Alex See +3 more | 2020-03-31 |
| 10446607 | Integrated two-terminal device with logic device for embedded application | Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Hai Cong, Alex See +3 more | 2019-10-15 |
| 10439129 | Shielded MRAM cell | Dimitri Houssameddine, Chenchen Jacob Wang, Bin Liu | 2019-10-08 |
| 10224338 | Cost-effective method to form a reliable memory device with selective silicidation and resulting device | — | 2019-03-05 |
| 10062641 | Integrated circuits including a dummy metal feature and methods of forming the same | Haifeng Sheng, Shifeng Zhao, Juan Boon Tan | 2018-08-28 |
| 9929165 | Method for producing integrated circuit memory cells with less dedicated lithographic steps | Laiqiang Luo, Yu Jin Eugene Kong, Daxiang Wang, Fan Zhang, Danny Pak-Chum Shum +4 more | 2018-03-27 |
| 9905282 | Top electrode dome formation | Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan | 2018-02-27 |
| 9793208 | Plasma discharge path | Haifeng Sheng, Juan Boon Tan, Wanbing Yi, Daxiang Wang | 2017-10-17 |
| 9236391 | Method of forming split-gate cell for non-volative memory devices | Yu-Chung Chen, Huajun Liu, Siow Lee Chwa, Yanxia Shao, Yoke Leng Lim | 2016-01-12 |
| 9111866 | Method of forming split-gate cell for non-volative memory devices | Yu-Chung Chen, Huajun Liu, Siow Lee Chwa, Yanxia Shao, Yoke Leng Lim | 2015-08-18 |
| 8957523 | Dielectric posts in metal layers | Fan Zhang, Wei Shao, Juan Boon Tan, Yeow Kheng Lim, Mahesh Bhatkar | 2015-02-17 |
| 8759947 | Back-side MOM/MIM devices | Juan Boon Tan, Yeow Kheng Lim, Shao Ning Yuan, Shunqiang Gong | 2014-06-24 |
| 8716856 | Device with integrated power supply | Juan Boon Tan, Yeow Kheng Lim, Wei Liu, Shunqiang Gong | 2014-05-06 |
| 8569173 | Methods of protecting elevated polysilicon structures during etching processes | Liang Li, Huang Liu, Alex See, Xue Song Rao, Peng Zhou | 2013-10-29 |
| 6762085 | Method of forming a high performance and low cost CMOS device | Jia Zhen Zheng, Liang-Choo Hsia, Eng Hua Lim, Simon Chooi, Chew Hoe Ang | 2004-07-13 |
| 6734082 | Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape | Jia Zhen Zheng, Chew Hoe Ang | 2004-05-11 |
| 6586314 | Method of forming shallow trench isolation regions with improved corner rounding | Liang-Choo Hsia, Jia Zhen Zheng, Chew Hoe Ang | 2003-07-01 |
| 6350661 | Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts | Chong Wee Lim, Eng Hua Lim, Kong Hean Lee, Chun Hui Low | 2002-02-26 |
| 6297126 | Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts | Chong Wee Lim, Eng Hua Lim, Kong Hean Lee, Chun Hui Low | 2001-10-02 |
| 6271133 | Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication | Chong Wee Lim, Eng Hua Lim, Kin Leong Pey, Chun Hui Low | 2001-08-07 |
| 6265302 | Partially recessed shallow trench isolation method for fabricating borderless contacts | Chong Wee Lim, Eng Hua Lim, Kong Hean Lee, Chun Hui Low | 2001-07-24 |
| 6228727 | Method to form shallow trench isolations with rounded corners and reduced trench oxide recess | Chong Wee Lim, Eng Hua Lim, Kong Hean Lee, Chun Hui Low | 2001-05-08 |
| 6165871 | Method of making low-leakage architecture for sub-0.18 .mu.m salicided CMOS device | Eng Hua Lim, Chong Wee Lim, Kong Hean Lee, Pei Ching Lee | 2000-12-26 |