Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9318378 | Slot designs in wide metal lines | Alex See, Tae Jong Lee, David Vigar, Liang-Choo Hsia, Kin Leong Pey | 2016-04-19 |
| 8957523 | Dielectric posts in metal layers | Fan Zhang, Wei Shao, Juan Boon Tan, Mahesh Bhatkar, Soh Yun Siah | 2015-02-17 |
| 8860185 | Crack-arresting structure for through-silicon vias | Shaoning Yuan, Yue Kang Lu, Juan Boon Tan | 2014-10-14 |
| 8766454 | Integrated circuit with self-aligned line and via | Randall Cher Liang Cha, Alex See, Wang Ling Goh | 2014-07-01 |
| 8759947 | Back-side MOM/MIM devices | Juan Boon Tan, Shao Ning Yuan, Soh Yun Siah, Shunqiang Gong | 2014-06-24 |
| 8716856 | Device with integrated power supply | Juan Boon Tan, Soh Yun Siah, Wei Liu, Shunqiang Gong | 2014-05-06 |
| 8466062 | TSV backside processing using copper damascene interconnect technology | Yue Kang Lu, Shaoning Yuan, Juan Boon Tan | 2013-06-18 |
| 8358007 | Integrated circuit system employing low-k dielectrics and method of manufacture thereof | Dong Kyun Sohn, Wuping Liu, Fan Zhang, Juan Boon Tan, Jing Hui Li +3 more | 2013-01-22 |
| 7790617 | Formation of metal silicide layer over copper interconnect for reliability enhancement | Wei Lu, Liang-Choo Hsia, Jyoti Gupta, Chim Seng Seet, Hao Zhang | 2010-09-07 |
| 7372156 | Method to fabricate aligned dual damascene openings | Wuping Liu, Tae Jong Lee, Bei Chao Zhang, Juan Boon Tan, Alan Cuthbertson +1 more | 2008-05-13 |
| 7253097 | Integrated circuit system using dual damascene process | Chim Seng Seet, Tae Jong Lee, Liang-Choo Hsia, Kin Leong Pey | 2007-08-07 |
| 7119010 | Integrated circuit with self-aligned line and via and manufacturing method therefor | Randall Cher Liang Cha, Alex See, Wang Ling Goh | 2006-10-10 |
| 6967156 | Method to fabricate aligned dual damascene openings | Wuping Liu, Tae Jong Lee, Bei Chao Zhang, Juan Boon Tan, Alan Cuthbertson +1 more | 2005-11-22 |
| 6849928 | Dual silicon-on-insulator device wafer die | Randall Cher Liang Cha, Alex See, Tae Jong Lee, Wang Ling Goh | 2005-02-01 |
| 6780691 | Method to fabricate elevated source/drain transistor with large area for silicidation | Randall Cher Liang Cha, Alex See, Jia Zhen Zheng | 2004-08-24 |
| 6613652 | Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance | Randall Cher Liang Cha, Alex See, Tae Jong Lee, Wang Ling Goh | 2003-09-02 |
| 6558994 | Dual silicon-on-insulator device wafer die | Randall Cher Liang Cha, Alex See, Tae Jong Lee, Wang Ling Goh | 2003-05-06 |
| 6518133 | Method for fabricating a small dimensional gate with elevated source/drain structures | Alex See, Cher Liang Cha | 2003-02-11 |
| 6472697 | Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application | Randall Cher Liang Cha, Alex See, Wang Ling Goh, Victor Lim | 2002-10-29 |
| 6468880 | Method for fabricating complementary silicon on insulator devices using wafer bonding | Randall Cher Liang Cha, Alex See, Tae Jong Lee, Wang Ling Goh | 2002-10-22 |
| 6432797 | Simplified method to reduce or eliminate STI oxide divots | Randall Cher Liang Cha, Tae Jong Lee, Alex See, Lap Chan | 2002-08-13 |
| 6399471 | Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application | Randall Cher Liang Cha, Alex See, Wang Ling Goh, Victor Lim | 2002-06-04 |
| 6380084 | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling | Alex See, Cher Liang Cha, Subhash Gupta, Wang Ling Goh, Man Siu Tse | 2002-04-30 |
| 6355563 | Versatile copper-wiring layout design with low-k dielectric integration | Randall Cher Liang Cha, Alex See, Tae Jong Lee, Lap Chan | 2002-03-12 |
| 6319767 | Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique | Randall Cher Liang Cha, Tae Jong Lee, Alex See, Lap Chan | 2001-11-20 |