CC

Cher Liang Cha

CM Chartered Semiconductor Manufacturing: 26 patents #25 of 840Top 3%
NS National University Of Singapore: 9 patents #23 of 1,623Top 2%
IM Institute Of Microelectronics: 1 patents #60 of 153Top 40%
NS Nanyang Technological University Of Singapore: 1 patents #4 of 17Top 25%
📍 Singapore, SG: #206 of 13,971 inventorsTop 2%
Overall (All Time): #156,156 of 4,157,543Top 4%
26
Patents All Time

Issued Patents All Time

Showing 1–25 of 26 patents

Patent #TitleCo-InventorsDate
7573081 Method to fabricate horizontal air columns underneath metal inductor Lap Chan, Kok Wai Chew, Chee Tee Chua 2009-08-11
7112866 Method to form a cross network of air gaps within IMD layer Lap Chan, Kheng Chok Tee 2006-09-26
7105420 Method to fabricate horizontal air columns underneath metal inductor Lap Chan, Kok Wai Chew, Chee Tee Chua 2006-09-12
6764914 Method of forming a high K metallic dielectric layer Alex See, Shyue Fong Quek, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong +2 more 2004-07-20
6730571 Method to form a cross network of air gaps within IMD layer Lap Chan, Kheng Chok Tee 2004-05-04
6680239 Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant Kok Keng Ong, Alex See, Lap Chan 2004-01-20
6610575 Forming dual gate oxide thickness on vertical transistors by ion implantation Chew Hoe Ang, Eng Hua Lim, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more 2003-08-26
6605501 Method of fabricating CMOS device with dual gate electrode Chew Hoe Ang, Eng Hua Lim, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou 2003-08-12
6566209 Method to form shallow junction transistors while eliminating shorts due to junction spiking Lap Chan, Ravishankar Sundaresan 2003-05-20
6531750 Shallow junction transistors which eliminating shorts due to junction spiking Lap Chan, Ravishankar Sundaresan 2003-03-11
6518133 Method for fabricating a small dimensional gate with elevated source/drain structures Alex See, Yeow Kheng Lim 2003-02-11
6501122 Flash device having a large planar area ono interpoly dielectric Lap Chan 2002-12-31
6492242 Method of forming of high K metallic dielectric layer Alex See, Shyuz Fong Quek, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong +2 more 2002-12-10
6483148 Self-aligned elevated transistor Lap Chan 2002-11-19
6380084 Method to form high performance copper damascene interconnects by de-coupling via and metal line filling Yeow Kheng Lim, Alex See, Subhash Gupta, Wang Ling Goh, Man Siu Tse 2002-04-30
6326272 Method for forming self-aligned elevated transistor Lap Chan 2001-12-04
6303418 Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer Alex See, Lap Chan 2001-10-16
6297109 Method to form shallow junction transistors while eliminating shorts due to junction spiking Lap Chan, Ravishankar Sundaresan 2001-10-02
6252277 Embedded polysilicon gate MOSFET Lap Chan, Eng Fong Chor, Gong Hao, Teck Koon Lee 2001-06-26
6221727 Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology Lap Chan, Johnny Kok Wai Chew, Chee Tee Chua 2001-04-24
6207534 Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing Lap Chan, Teck Koon Lee 2001-03-27
6150232 Formation of low k dielectric Lap Chan, Kok Keng Ong, Kheng Chok Tee 2000-11-21
6140197 Method of making spiral-type RF inductors having a high quality factor (Q) Shau-Fu Sanford Chu, Kok Wai Chew, Chee Tee Chua 2000-10-31
6096604 Production of reversed flash memory device Anqing Zhang, Zhifeng Xie, Eng Fong Chor 2000-08-01
6064201 Method and apparatus to image metallic patches embedded in a non-metal surface Hao Gong, Eng Fong Chor, Lap Chan 2000-05-16