Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9064084 | Topography driven OPC and lithography flow | Ushasree Katakamsetty, Yang Qing, Wee Kwong Yeo, Chiu Wing Hui, Valerio Perez | 2015-06-23 |
| 8898597 | Etch failure prediction based on wafer resist top loss | Qing Yang, Gek Soon Chua, Yee Mei Foong, Dong-Qing Zhang, Yun Tang | 2014-11-25 |
| 6963113 | Method of body contact for SOI MOSFET | Ting Cheong Ang, Sang Yee Loong, Jun Song | 2005-11-08 |
| 6803314 | Double-layered low dielectric constant dielectric dual damascene method | Ting Cheong Ang, Yee Chong Wong, Sang Yee Long | 2004-10-12 |
| 6787422 | Method of body contact for SOI mosfet | Ting Cheong Ang, Sang Yee Loong, Jun Song | 2004-09-07 |
| 6764914 | Method of forming a high K metallic dielectric layer | Alex See, Cher Liang Cha, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong +2 more | 2004-07-20 |
| 6737739 | Method of vacuum packaging a semiconductor device assembly | Ting Cheong Ang, Duay Ing Ong, Sang Yee Loong | 2004-05-18 |
| 6653674 | Vertical source/drain contact semiconductor | Ting Cheong Ang, Sang Yee Loong, Puay Ing Ong | 2003-11-25 |
| 6611024 | Method of forming PID protection diode for SOI wafer | Ting Cheong Ang, Sang Yee Loong, Jun Song | 2003-08-26 |
| 6582856 | Simplified method of fabricating a rim phase shift mask | Ting Cheong Ang, Jun Song, Sang Yee Loong | 2003-06-24 |
| 6495399 | Method of vacuum packaging a semiconductor device assembly | Ting Cheong Ang, Duay Ing Ong, Sang Yee Loong | 2002-12-17 |
| 6492726 | Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection | Ying-Keung Leung, Sang Yee Loong, Ting Cheong Ang | 2002-12-10 |
| 6486515 | ESD protection network used for SOI technology | Song Jun, Ting Cheong Ang, Sang Yee Loong | 2002-11-26 |
| 6465296 | Vertical source/drain contact semiconductor | Ting Cheong Ang, Sang Yee Loong, Puay Ing Ong | 2002-10-15 |
| 6455384 | Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacers | Ting Cheong Ang, Jun Song, Xing Yu | 2002-09-24 |
| 6416909 | Alternating phase shift mask and method for fabricating the alignment monitor | Ting Cheong Ang, Swee Hong Choo, Sang Yee Loong | 2002-07-09 |
| 6406948 | Method for forming an ESD protection network for SOI technology with the ESD device formed in an underlying silicon substrate | Song Jun, Ting Cheong Ang, Sang Yee Loong | 2002-06-18 |
| 6406994 | Triple-layered low dielectric constant dielectric dual damascene approach | Ting Cheong Ang, Yee Chong Wong, Sang Yee Loong | 2002-06-18 |
| 6399431 | ESD protection device for SOI technology | Jun Song, Ting Cheong Ang, Sang Yee Loong | 2002-06-04 |
| 6376319 | Process to fabricate a source-drain extension | Ting Cheong Ang, Jun Song, Xing Yu | 2002-04-23 |
| 6376379 | Method of hard mask patterning | Ting Cheong Ang, Jun Song, Sang Yee Loong | 2002-04-23 |
| 6329253 | Thick oxide MOS device used in ESD protection circuit | Jun Song, Yonqzang Zhang, Ting Cheong Ang, Jun Cai, Puay Ing Ong | 2001-12-11 |
| 6303414 | Method of forming PID protection diode for SOI wafer | Ting Cheong Ang, Sang Yee Loong, Jun Song | 2001-10-16 |
| 6284609 | Method to fabricate a MOSFET using selective epitaxial growth to form lightly doped source/drain regions | Ting Cheong Ang, Puay Ing Ong, Sang Yee Loong | 2001-09-04 |
| 6275089 | Low voltage controllable transient trigger network for ESD protection | Jun Song, Ting Cheong Ang, Lap Chan | 2001-08-14 |