Issued Patents All Time
Showing 25 most recent of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9627219 | CMP wafer edge control of dielectric | Lei Wang, Xuesong Rao, Wei Lu | 2017-04-18 |
| 9349654 | Isolation for embedded devices | Liang Li, Xuesong Rao, Martina Damayanti, Wei Lu, Yoke Leng Lim | 2016-05-24 |
| 9242338 | CMP head structure | Benfu Lin, Lei Wang, Xuesong Rao, Wei Lu | 2016-01-26 |
| 9242341 | CMP head structure | Benfu Lin, Wei Lu | 2016-01-26 |
| 9230886 | Method for forming through silicon via with wafer backside protection | Lup San Leong, Zheng Zou, Hai Cong, Xuesong Rao, Yun Ling Tan +1 more | 2016-01-05 |
| 9034720 | Litho scanner alignment signal improvement | Hui-Hsien Liu, Wen-Zhan Zhou, Zheng Zou, Qun Ying Lin | 2015-05-19 |
| 9023725 | Filament free silicide formation | Kwee Liang Yeo, Chim Seng Seet, Zheng Zou | 2015-05-05 |
| 8940637 | Method for forming through silicon via with wafer backside protection | Lup San Leong, Zheng Zou, Hai Cong, Xuesong Rao, Yun Ling Tan +1 more | 2015-01-27 |
| 8852968 | STI CMP under polish monitoring | Liang Li, Zheng Zou, Huang Liu | 2014-10-07 |
| 8836139 | CD control | Zheng Zou, Huang Liu, Hai Cong | 2014-09-16 |
| 8828858 | Spacer profile engineering using films with continuously increased etch rate from inner to outer surface | Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Yun Ling Tan +2 more | 2014-09-09 |
| 8518775 | Integration of eNVM, RMG, and HKMG modules | Huang Liu, Hai Cong, Zheng Zou | 2013-08-27 |
| 8492236 | Step-like spacer profile | Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Yun Ling Tan +3 more | 2013-07-23 |
| 8415236 | Methods for reducing loading effects during film formation | Han-Guan Chew, Jinping Liu, Mei Sheng Zhou | 2013-04-09 |
| 8354347 | Method of forming high-k dielectric stop layer for contact hole opening | Jianhui Ye, Huang Liu, Wei Lu, Chun Hui Low, Chim Seng Seet +2 more | 2013-01-15 |
| 7112499 | Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal | Chyiu Hyia Poon, Leng Seow Tan, Byung Jin Cho, Mousumi Bhat | 2006-09-26 |
| 7091092 | Process flow for a performance enhanced MOSFET with self-aligned, recessed channel | Sneedharan Pillai Sneelal, Francis Poh, James Yong Meng Lee, C. K. Lau, Ganesh Samudra | 2006-08-15 |
| 7030451 | Method and apparatus for performing nickel salicidation | Pooi See Lee, Kin Leong Pey, Lap Chan | 2006-04-18 |
| 6905964 | Method of fabricating self-aligned metal barriers by atomic layer deposition on the copper layer | Boon Kiat Lim | 2005-06-14 |
| 6899857 | Method for forming a region of low dielectric constant nanoporous material using a microemulsion technique | Soo Choi Pheng, Lap Chan, Wang Cui Yang, Siew Yong Kong | 2005-05-31 |
| 6897118 | Method of multiple pulse laser annealing to activate ultra-shallow junctions | Chyiu Hyia Poon, Byung Jin Cho, Yong Lu, Mousumi Bhat | 2005-05-24 |
| 6890854 | Method and apparatus for performing nickel salicidation | Pooi See Lee, Kin Leong Pey, Lap Chan | 2005-05-10 |
| 6878623 | Technique to achieve thick silicide film for ultra-shallow junctions | Cheng Tan, Randall Cher Liang Cha, Lap Chan | 2005-04-12 |
| 6780691 | Method to fabricate elevated source/drain transistor with large area for silicidation | Randall Cher Liang Cha, Yeow Kheng Lim, Jia Zhen Zheng | 2004-08-24 |
| 6777329 | Method to form C54 TiSi2 for IC device fabrication | Shaoyin Chen, Ze Shen, Lap Chan | 2004-08-17 |