Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10608046 | Integrated two-terminal device with logic device for embedded application | Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Soh Yun Siah, Alex See +3 more | 2020-03-31 |
| 10510825 | Metal-insulator-metal capacitor with improved time-dependent dielectric breakdown | Zhehui Wang, Ramadas Nambatyathu | 2019-12-17 |
| 10461247 | Integrated magnetic random access memory with logic device having low-K interconnects | Danny Pak-Chum Shum, Juan Boon Tan, Yi Jiang, Wanbing Yi, Francis Poh | 2019-10-29 |
| 10446607 | Integrated two-terminal device with logic device for embedded application | Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Soh Yun Siah, Alex See +3 more | 2019-10-15 |
| 10115625 | Methods for removal of hard mask | Liang Li, Yun Ling Tan, Changwei Pei, Alex See | 2018-10-30 |
| 10103097 | CD control | Zheng Zou, Alex See, Huang Liu | 2018-10-16 |
| 9972775 | Integrated magnetic random access memory with logic device having low-k interconnects | Danny Pak-Chum Shum, Juan Boon Tan, Yi Jiang, Wanbing Yi, Francis Poh | 2018-05-15 |
| 9805971 | Method of forming a via contact | Rui Li, Chin Chuan Neo | 2017-10-31 |
| 9564575 | Dual encapsulation integration scheme for fabricating integrated circuits with magnetic random access memory structures | Danny Pak-Chum Shum, Yi Jiang, Juan Boon Tan | 2017-02-07 |
| 9520299 | Etch bias control | Wanbing Yi, Chin Chuan Neo, Kin Wai Tang, Weining Li, Juan Boon Tan | 2016-12-13 |
| 9437550 | TSV without zero alignment marks | Shunqiang Gong, Juan Boon Tan, Wei Liu | 2016-09-06 |
| 9230886 | Method for forming through silicon via with wafer backside protection | Lup San Leong, Zheng Zou, Alex See, Xuesong Rao, Yun Ling Tan +1 more | 2016-01-05 |
| 8987134 | Reliable interconnect for semiconductor device | Zhehui Wang, Kwee Liang Yeo, Huang Liu, Wen-Zhan Zhou | 2015-03-24 |
| 8940637 | Method for forming through silicon via with wafer backside protection | Lup San Leong, Zheng Zou, Alex See, Xuesong Rao, Yun Ling Tan +1 more | 2015-01-27 |
| 8836139 | CD control | Zheng Zou, Alex See, Huang Liu | 2014-09-16 |
| 8828858 | Spacer profile engineering using films with continuously increased etch rate from inner to outer surface | Xuesong Rao, Chim Seng Seet, Zheng Zou, Alex See, Yun Ling Tan +2 more | 2014-09-09 |
| 8737061 | Heat dissipating apparatus | Chien-Lung Chang | 2014-05-27 |
| 8546873 | Integrated circuit and method of fabrication thereof | Jinping Liu, Binbin Zhou, Alex See, Mei Sheng Zhou, Liang-Choo Hsia | 2013-10-01 |
| 8518775 | Integration of eNVM, RMG, and HKMG modules | Huang Liu, Alex See, Zheng Zou | 2013-08-27 |
| 8492236 | Step-like spacer profile | Xuesong Rao, Chim Seng Seet, Zheng Zou, Alex See, Yun Ling Tan +3 more | 2013-07-23 |
| 8394724 | Processing with reduced line end shortening ratio | Wei Loong Loh, Krishan Gopal, Xin Ji Zhang, Mei Sheng Zhou, Pradeep Ramachandramurthy Yelehanka | 2013-03-12 |
| 8293545 | Critical dimension for trench and vias | Yan Shan Li, Chun Hui Low, Yelehanka Ramachandramurthy Pradeep, Liang-Choo Hsia | 2012-10-23 |
| 8058123 | Integrated circuit and method of fabrication thereof | Jinping Liu, Binbin Zhou, Alex See, Mei Sheng Zhou, Liang-Choo Hsia | 2011-11-15 |
| 7960283 | Method for reducing silicide defects in integrated circuits | Jeff Jianhui Ye, Huang Liu, Alex See, Wei Lu, Hui Peng Koh +2 more | 2011-06-14 |
| 7892900 | Integrated circuit system employing sacrificial spacers | Huang Liu, Wei Lu, Alex See, Hui Peng Koh, Meisheng Zhou | 2011-02-22 |