Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12292913 | Automatic industry classification method and system | Kai Cao, Minyue Zhang | 2025-05-06 |
| 11847152 | Patent evaluation method and system that aggregate patents based on technical clustering | Minyue Zhang, Kai Cao, Yudan Lv, Yulin Zhou, Jiantao Li +1 more | 2023-12-19 |
| 9520299 | Etch bias control | Wanbing Yi, Chin Chuan Neo, Hai Cong, Kin Wai Tang, Juan Boon Tan | 2016-12-13 |
| 9407844 | Hardware partial frame elimination in a sensor interface | — | 2016-08-02 |
| 8817132 | Hardware partial frame elimination in a sensor interface | — | 2014-08-26 |
| 8261034 | Memory system for cascading region-based filters | — | 2012-09-04 |
| 8236646 | Non-volatile memory manufacturing method using STI trench implantation | Tze Ho Simon Chan, Elgin Quek, Jia Zhen Zheng, Pradeep Ramachandramurthy Yelehanka, Tommy Lai | 2012-08-07 |
| 7501683 | Integrated circuit with protected implantation profiles and method for the formation thereof | Tommy Lai, Pradeep Ramachandramurthy Yelehanka, Jia Zhen Zheng | 2009-03-10 |
| 7285804 | Thyristor-based SRAM | Elgin Quek, Jia Zhen Zheng, Pradeep Ramachandramurthy Yelehanka | 2007-10-23 |
| 7183590 | Horizontal tram | Jia Zhen Zheng, Tze Ho Simon Chan, Pradeep Ramachandramurthy Yelehanka | 2007-02-27 |
| 7148522 | Thyristor-based SRAM | Elgin Quek, Pradeep Ramachandramurthy Yelehanka, Jia Zhen Zheng, Tommy Lai | 2006-12-12 |
| 7081378 | Horizontal TRAM and method for the fabrication thereof | Jia Zhen Zheng, Tze Ho Simon Chan, Pradeep Ramachandramurthy Yelehanka | 2006-07-25 |
| 7067362 | Integrated circuit with protected implantation profiles and method for the formation thereof | Tommy Lai, Pradeep Ramachandramurthy Yelehanka, Jia Zhen Zheng | 2006-06-27 |
| 7015101 | Multi-level gate SONOS flash memory device with high voltage oxide and method for the fabrication thereof | Jia Zhen Zheng, Pradeep Ramachandramurthy Yelehanka | 2006-03-21 |
| 6897111 | Method using quasi-planar double gated fin field effect transistor process for the fabrication of a thyristor-based static read/write random-access memory | Elgin Quek, Jia Zhen Zheng, Pradeep Ramachandramurthy Yelehanka | 2005-05-24 |
| 6849481 | Thyristor-based SRAM and method for the fabrication thereof | Elgin Quek, Pradeep Ramachandramurthy Yelehanka, Jia Zhen Zheng, Tommy Lai | 2005-02-01 |
| 6649461 | Method of angle implant to improve transistor reverse narrow width effect | Tommy Lai, Yung-Tao Lin | 2003-11-18 |
| 6521540 | Method for making self-aligned contacts to source/drain without a hard mask layer | — | 2003-02-18 |
| 6509264 | Method to form self-aligned silicide with reduced sheet resistance | Yung-Tao Lin | 2003-01-21 |
| 6376298 | Layout method for scalable design of the aggressive RAM cells using a poly-cap mask | Yung-Tao Lin | 2002-04-23 |
| 6177304 | Self-aligned contact process using a poly-cap mask | Yung-Tao Lin, Mau Lam Lai, Tin Tin Wee | 2001-01-23 |
| 6093602 | Method to form polycide local interconnects between narrowly-spaced features while eliminating stringers | Lin Tao, RAMACHANDRAMURTHY PRADEEP YELEHANKA, Tin Tin Wee | 2000-07-25 |