Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11380675 | Integrated stacked ESD network in trench for trench DMOS | Yeuk Yin Mong, Duc Chau | 2022-07-05 |
| 9704986 | VDMOS having shielding gate electrodes in trenches and method of making the same | Yeuk Yin Mong, Duc Chau | 2017-07-11 |
| 9466707 | Planar mosfets and methods of fabrication, charge retention | Yeuk Yin Mong, Duc Chau | 2016-10-11 |
| 7126197 | Power MOSFET and methods of making same | Kin On Johnny Sin | 2006-10-24 |
| 6835609 | Method of forming double-gate semiconductor-on-insulator (SOI) transistors | Yong Meng Lee, Da Jin, David Vigar, Siow Lee Chwa | 2004-12-28 |
| 6177304 | Self-aligned contact process using a poly-cap mask | Weining Li, Yung-Tao Lin, Tin Tin Wee | 2001-01-23 |