Issued Patents All Time
Showing 1–25 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12366603 | Structure and method for testing of PIC with an upturned mirror | Lucas Soldano, Jing Yang, Suresh Venkatesan | 2025-07-22 |
| 12105141 | Structure and method for testing of PIC with an upturned mirror | Lucas Soldano, Jing Yang, Suresh Venkatesan | 2024-10-01 |
| 11921156 | Structure and method for testing of PIC with an upturned mirror | Lucas Soldano, Jing Yang, Suresh Venkatesan | 2024-03-05 |
| 9607989 | Forming self-aligned NiSi placement with improved performance and yield | Xusheng Wu, Yue Hu, Xin-Yong WANG, Wen-Pin Peng, Lun Zhao +1 more | 2017-03-28 |
| 9524911 | Method for creating self-aligned SDB for minimum gate-junction pitch and epitaxy formation in a fin-type IC device | Hao-Cheng Tsai, Min-hwa Chi | 2016-12-20 |
| 9385030 | Spacer to prevent source-drain contact encroachment | Yue Hu, Wen-Pin Peng | 2016-07-05 |
| 9209258 | Depositing an etch stop layer before a dummy cap layer to improve gate performance | Feng Zhou, Tien Ying Luo, Haiting Wang, Padmaja NAGAIAH, Jean-Baptiste Laloe +1 more | 2015-12-08 |
| 9202697 | Forming a gate by depositing a thin barrier layer on a titanium nitride cap | Tien Ying Luo, Feng Zhou, Yan Ping SHEN, Haiting Wang, Haoran SHI +2 more | 2015-12-01 |
| 9147572 | Using sacrificial oxide layer for gate length tuning and resulting device | Ashish Jha, Haiting Wang, Meng Luo | 2015-09-29 |
| 9123783 | Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection | Xin-Yong WANG, Changyong Xiao, Yue Hu, Meng Luo, Jialin Weng +2 more | 2015-09-01 |
| 8859388 | Sealed shallow trench isolation region | Michael V. Aquilino, Xiang Hu, Daniel Jaeger, Byeong Y. Kim, Ying Li +1 more | 2014-10-14 |
| 8716081 | Capacitor top plate over source/drain to form a 1T memory device | Lee-Wee Teo, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee +2 more | 2014-05-06 |
| 8624329 | Spacer-less low-K dielectric processes | Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan +3 more | 2014-01-07 |
| 8623714 | Spacer protection and electrical connection for array device | Jae-Eun Park, Weipeng Li, Deleep R. Nair, M. Dean Sciacca, Voon-Yew Thean +2 more | 2014-01-07 |
| 8274115 | Hybrid orientation substrate with stress layer | Lee-Wee Teo, Chung Woh Lai, Johnny Widodo, Shyue Seng Tan, Shailendra Mishra +2 more | 2012-09-25 |
| 8106462 | Balancing NFET and PFET performance using straining layers | Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony +8 more | 2012-01-31 |
| 8053327 | Method of manufacture of an integrated circuit system with self-aligned isolation structures | Shailendra Mishra, Lee-Wee Teo, Zhao Lun, Chung Woh Lai, Shyue Seng Tan +2 more | 2011-11-08 |
| 7999325 | Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS | Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan +3 more | 2011-08-16 |
| 7977185 | Method and apparatus for post silicide spacer removal | Brian J. Greene, Chung Woh Lai, Wenhe Lin, Siddhartha Panda, Kern Rim +1 more | 2011-07-12 |
| 7932178 | Integrated circuit having a plurality of MOSFET devices | Lee-Wee Teo, Jeffrey Chee, Shyue Seng Tan, Chung Woh Lai, Johnny Widodo +2 more | 2011-04-26 |
| 7893502 | Threshold voltage improvement employing fluorine implantation and adjustment oxide layer | Weipeng Li, Dae-Gyu Park, Melanie J. Sherony, Jin-Ping Han | 2011-02-22 |
| 7737009 | Method of implanting a non-dopant atom into a semiconductor device | Richard Lindsay, Manfred Eller | 2010-06-15 |
| 7659174 | Method to enhance device performance with selective stress relief | Haining Yang, Victor Chan | 2010-02-09 |
| 7615427 | Spacer-less low-k dielectric processes | Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan +3 more | 2009-11-10 |
| 7598572 | Silicided polysilicon spacer for enhanced contact area | Thomas W. Dyer, Sunfei Fang, Ja-Hum Ku | 2009-10-06 |